 bart
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da2bff2ea2
Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking.
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1 gadu atpakaļ |
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bart
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308cc6a90d
Fixed SDRAM controller by setting phase shift to 180 degrees.
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2 gadi atpakaļ |
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bart
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 gadi atpakaļ |
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bart
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b74702c915
Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram
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2 gadi atpakaļ |
