 bart
|
b6831c4209
Added L2 cache (no L1 for now) between CPU and SDRAM controller. No noticable performance difference, can likely be optimized further to reduce cache hit latency.
|
1 year ago |
|
bart
|
1026f4776c
Cleaned up some files
|
2 years ago |
|
bart
|
207413dd90
Assembler only needs Int: function, fixed position of program lenght. Ported ROM and UART bootloader over from FPGC5. Updated documentation on interrupts. Added resets. Fixed bug in MU. Increased stack size. Tested everything in hardware. Probably some other fixes and things I forgot.
|
2 years ago |
