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bart
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FPGC6
réplica de
https://github.com/bartpleiter/FPGC6
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d2b53bb5e8
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EP4CE15
cpu100mhz
fast-cpu-pipeline
main
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bart
9662964536
Added back scripts for converting to spi.txt. Tested code to run from SPI flash, fixed cycle delay for SPI flash in output latch in MU which caused the bus_q to arrive a cycle later than bus_done.
%!s(int64=2) %!d(string=hai) anos