提交歷史

作者 SHA1 備註 提交日期
  bart 7e81e7fa17 Added files missing from last commit (L1I cache). 1 年之前
  bart 207413dd90 Assembler only needs Int: function, fixed position of program lenght. Ported ROM and UART bootloader over from FPGC5. Updated documentation on interrupts. Added resets. Fixed bug in MU. Increased stack size. Tested everything in hardware. Probably some other fixes and things I forgot. 2 年之前
  bart 69e83fb855 Fully implemented interrupts in verilog. Return address appears to work fine, but might need some further testing for different delays in the pipeline. 2 年之前
  bart e493a27ab4 Started on interrupts. Triggering seems to work, reti still needs to be implemented 2 年之前
  bart ced78a8cbf Fixed signed number bug in assembler, updated documentation about signed branches 2 年之前
  bart 1cf78e1fab Added and updated the assembler (python version) 2 年之前
  bart b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram 2 年之前
  bart f5bc168700 Added DataMem to MU via Arbiter, fixed several bugs while doing this. Works with test code, but will most likely still contain bugs in certain cases. 2 年之前
  bart 0e533922fb Connected instruction memory to the MU via the arbiter 2 年之前
  bart 916054063a Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design 2 年之前
  Bart 43293f6ca4 Deleted some old memory files 2 年之前
  Bart 55f619efae Initial commit with some empty Verilog template code from FPGC5 2 年之前