提交历史

作者 SHA1 备注 提交日期
  bart f78729ea77 Fixed L2 cache state machine issue which was only present in the previous commit. 1 年之前
  bart 88681ec5d0 New arbiter that further improves performance by removing latency for instruction memory access. Created instability again, which I found to be caused by bad interrupt timings. Fixed by changing the interruptValid wire to use branch_MEM for alignment. I do not know why this fixed all problems as it is very hard to simulate this issue. L1 cache should be possible again! 1 年之前
  bart add43b75da L2 cache at 100MHz now greatly increases performance. Attempted to create l1i and l1d cache, but becomes unstable and the issue is difficult to similate/replicate. Therefore, all l1 cache is now bypassed and the code can be found in l1cacheUnstable.v. As no l1 cache anymore, I removed some ccache statements to increase performance as this instruction currently does nothing. 1 年之前
  bart 7e81e7fa17 Added files missing from last commit (L1I cache). 1 年之前
  bart dfb3bbb48e Added L1D cache. Currently only works stable when valid bit is set 0 on WRITE. Valid bit 1 after cache miss read works fine for some reason. 1 年之前
  bart b6831c4209 Added L2 cache (no L1 for now) between CPU and SDRAM controller. No noticable performance difference, can likely be optimized further to reduce cache hit latency. 1 年之前
  bart 28bcde6466 New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases. 1 年之前
  bart 207413dd90 Assembler only needs Int: function, fixed position of program lenght. Ported ROM and UART bootloader over from FPGC5. Updated documentation on interrupts. Added resets. Fixed bug in MU. Increased stack size. Tested everything in hardware. Probably some other fixes and things I forgot. 2 年之前
  bart 9662964536 Added back scripts for converting to spi.txt. Tested code to run from SPI flash, fixed cycle delay for SPI flash in output latch in MU which caused the bus_q to arrive a cycle later than bus_done. 2 年之前
  Bart 43293f6ca4 Deleted some old memory files 2 年之前
  Bart 55f619efae Initial commit with some empty Verilog template code from FPGC5 2 年之前