bart/FPGC6

mirror de https://github.com/bartpleiter/FPGC6

Autor	SHA1 Mensagem	Data
bartpleiter	030e6c305e More tests for 100mhz	5 meses atrás
bart	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	2 anos atrás
bart	b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram	2 anos atrás