 bartpleiter
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030e6c305e
More tests for 100mhz
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há 5 meses atrás |
 bart
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0fd222280a
Added halfres rendering mode to gpu and mu. Added millis counter to mu. Raycaster now renders at half resolution and many improvements. Now at 40 to 70fps.
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há 1 ano atrás |
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bart
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4e7cdb1216
Changed pixelplane to 24 bit colors. Updated texture generator and raycaster to 24 bit color.
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há 1 ano atrás |
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bart
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69d109e653
Added hardware signed and unsigned integer division and modulo. Created simple integer calculator to test. Updated several programs and BDOS to use new division hardware while keeping software calculation as legacy functions.
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há 1 ano atrás |
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bart
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f3f3a43044
Added fixed-point signed divider to MU. Integrated into FPCALC.
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há 1 ano atrás |
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bart
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3af9eecaa9
Added signed fixed point multiplication to ALU.
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há 1 ano atrás |
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bart
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f78729ea77
Fixed L2 cache state machine issue which was only present in the previous commit.
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há 1 ano atrás |
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bart
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da2bff2ea2
Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking.
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há 1 ano atrás |
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bart
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2287e54c6b
Integrated valid bits into cache block ram. Reset now iteratively clears the entire cache. Allows for much lower FPGA usage and better timings. Should be able to greatly increase cache size as there is an abundance of BRAM.
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há 1 ano atrás |
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bart
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add43b75da
L2 cache at 100MHz now greatly increases performance. Attempted to create l1i and l1d cache, but becomes unstable and the issue is difficult to similate/replicate. Therefore, all l1 cache is now bypassed and the code can be found in l1cacheUnstable.v. As no l1 cache anymore, I removed some ccache statements to increase performance as this instruction currently does nothing.
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há 1 ano atrás |
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bart
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9a6bf3cd52
Improved reset for cache. Disabled l2 cache as it currently reduces performance. Added more CCache instructions to code, although likely not needed. Still instability issues when L1I cache is enabled.
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há 1 ano atrás |
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bart
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b6831c4209
Added L2 cache (no L1 for now) between CPU and SDRAM controller. No noticable performance difference, can likely be optimized further to reduce cache hit latency.
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há 1 ano atrás |
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bart
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28bcde6466
New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases.
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há 1 ano atrás |
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bart
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240770cb51
Progress on asm for bcc with new architecture. Started on SDRAM testbench for new controller.
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há 1 ano atrás |
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bart
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1a2f5e6c55
Added qws Quartus file.
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há 1 ano atrás |
