bart/FPGC6

spogulis no https://github.com/bartpleiter/FPGC6

Autors	SHA1 Ziņojums	Datums
bartpleiter	9438941e15 Initial setup to simulate 100mhz cpu in verilog testbench.	4 mēneši atpakaļ
bart	1026f4776c Cleaned up some files	2 gadi atpakaļ
bart	1cf78e1fab Added and updated the assembler (python version)	2 gadi atpakaļ