bart/FPGC6

镜像自地址 https://github.com/bartpleiter/FPGC6

作者	SHA1 备注	提交日期
bart	9662964536 Added back scripts for converting to spi.txt. Tested code to run from SPI flash, fixed cycle delay for SPI flash in output latch in MU which caused the bus_q to arrive a cycle later than bus_done.	2 年之前
Bart	43293f6ca4 Deleted some old memory files	2 年之前
Bart	55f619efae Initial commit with some empty Verilog template code from FPGC5	2 年之前