提交歷史

作者 SHA1 備註 提交日期
  bart b6831c4209 Added L2 cache (no L1 for now) between CPU and SDRAM controller. No noticable performance difference, can likely be optimized further to reduce cache hit latency. 1 年之前
  bart 69e83fb855 Fully implemented interrupts in verilog. Return address appears to work fine, but might need some further testing for different delays in the pipeline. 2 年之前
  bart e493a27ab4 Started on interrupts. Triggering seems to work, reti still needs to be implemented 2 年之前
  bart 9662964536 Added back scripts for converting to spi.txt. Tested code to run from SPI flash, fixed cycle delay for SPI flash in output latch in MU which caused the bus_q to arrive a cycle later than bus_done. 2 年之前
  bart 0e533922fb Connected instruction memory to the MU via the arbiter 2 年之前
  bart 916054063a Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design 2 年之前
  Bart fb0e4b363f Instruction memory can now have a delay without messing up the pipeline 2 年之前
  Bart 3714a90401 Forwarding now also works for data memory and also probably branches and other MEM operations. Fixed a bug in forwarding where EX was used instead of WB 2 年之前
  Bart 9da01544e7 Jump flush now seems to work. Made simple Quartus project to test in hardware and it seems to work fine there as well 2 年之前
  Bart a76e895a39 Started working on the CPU pipeline. Basic load, arith and jumps seem to work now. No hazard handling yet. 2 年之前
  Bart 7b0a44b7be Added testbench template with gtkw config 2 年之前
  Bart 55f619efae Initial commit with some empty Verilog template code from FPGC5 2 年之前