bart/FPGC6

Автор	SHA1 Съобщение	Дата
bart	6b31f51206 Added file and dir creation to BRFS.	преди 7 месеца
bart	b6831c4209 Added L2 cache (no L1 for now) between CPU and SDRAM controller. No noticable performance difference, can likely be optimized further to reduce cache hit latency.	преди 1 година
bart	1026f4776c Cleaned up some files	преди 2 години
bart	207413dd90 Assembler only needs Int: function, fixed position of program lenght. Ported ROM and UART bootloader over from FPGC5. Updated documentation on interrupts. Added resets. Fixed bug in MU. Increased stack size. Tested everything in hardware. Probably some other fixes and things I forgot.	преди 2 години