 b4rt-dev
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8d56c91fea
Added fast (but inaccurate) and accurate (but slow) option for UART flasher.
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2 lat temu |
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b4rt-dev
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118fe8b319
Improved new button check in USB keyboard driver of BDOS
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2 lat temu |
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b4rt-dev
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c4599a63cc
New documentation structure. Updated some documentation. Added relevant graphics scripts and files from FPGC5 repo.
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2 lat temu |
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bart
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52b5107bba
Created benchmarking tool which includes calculating digits of pi.
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2 lat temu |
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bart
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d55077792f
Updated BCC for B32P
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2 lat temu |
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bart
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6667e11cee
Updated documentation on assembler and BDOS.
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2 lat temu |
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bart
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4c9ea8dbde
Added list of things to add in documentation
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2 lat temu |
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bart
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1026f4776c
Cleaned up some files
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2 lat temu |
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bart
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b9bc26129d
Added gitattributes to ignore the huge UARTbootloader.asm file. Deleted old quartus test project.
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2 lat temu |
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bart
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9f74a9565f
Fixed more MU I/O bugs. Updated everything from BCC except the ASM to work on new CPU. Added back flasher programs. Fixed LOAD/HI bug by using unsigned const16 instead. Updated assembler including hotfix for FPGC jumping to addr3 after UART bootloader is done. FPGC6 now basically fully works again!
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2 lat temu |
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bart
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411c20ac98
Copied over BCC from FPGC5. No modifications yet.
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2 lat temu |
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bart
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58325c3b1d
Added Subl3 build files
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2 lat temu |
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bart
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207413dd90
Assembler only needs Int: function, fixed position of program lenght. Ported ROM and UART bootloader over from FPGC5. Updated documentation on interrupts. Added resets. Fixed bug in MU. Increased stack size. Tested everything in hardware. Probably some other fixes and things I forgot.
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2 lat temu |
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bart
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69e83fb855
Fully implemented interrupts in verilog. Return address appears to work fine, but might need some further testing for different delays in the pipeline.
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2 lat temu |
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bart
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e493a27ab4
Started on interrupts. Triggering seems to work, reti still needs to be implemented
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2 lat temu |
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bart
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ced78a8cbf
Fixed signed number bug in assembler, updated documentation about signed branches
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2 lat temu |
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bart
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1cf78e1fab
Added and updated the assembler (python version)
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2 lat temu |
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bart
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e2ec5415ce
Documentation update
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2 lat temu |
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bart
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baff95d710
Regbank and stack are now placed in BRAM, fixed combinational loop but further testing needed.
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2 lat temu |
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bart
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b74702c915
Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram
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2 lat temu |
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bart
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9662964536
Added back scripts for converting to spi.txt. Tested code to run from SPI flash, fixed cycle delay for SPI flash in output latch in MU which caused the bus_q to arrive a cycle later than bus_done.
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2 lat temu |
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bart
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f5bc168700
Added DataMem to MU via Arbiter, fixed several bugs while doing this. Works with test code, but will most likely still contain bugs in certain cases.
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2 lat temu |
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bart
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0e533922fb
Connected instruction memory to the MU via the arbiter
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2 lat temu |
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bart
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916054063a
Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design
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2 lat temu |
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bart
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6881f1be1d
Found bug where the next instruction after READ/WRITE is skipped if DataDelay but no InstrDelay
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2 lat temu |
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bart
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e8bc85adb6
Data memory now works with variable delays without breaking the pipeline
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2 lat temu |
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Bart
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fb0e4b363f
Instruction memory can now have a delay without messing up the pipeline
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2 lat temu |
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Bart
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3d9b4194f7
Added initial documentation
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2 lat temu |
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Bart
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302c69937e
Basic CPU design now done with afaik working hazard detection, forwarding and stalls. Tested in hardware on a EP4CE6 using two SSDisplays and dip switches to view the register content (and see if it matches the simulation). No interrupts yet as this can probably be done at a later stage.
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2 lat temu |
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Bart
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9ec3298860
Updated README and added licence so repo can go public now
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2 lat temu |
