 bart
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207413dd90
Assembler only needs Int: function, fixed position of program lenght. Ported ROM and UART bootloader over from FPGC5. Updated documentation on interrupts. Added resets. Fixed bug in MU. Increased stack size. Tested everything in hardware. Probably some other fixes and things I forgot.
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il y a 2 ans |
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bart
|
9662964536
Added back scripts for converting to spi.txt. Tested code to run from SPI flash, fixed cycle delay for SPI flash in output latch in MU which caused the bus_q to arrive a cycle later than bus_done.
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il y a 2 ans |
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bart
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916054063a
Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design
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il y a 2 ans |
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Bart
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43293f6ca4
Deleted some old memory files
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il y a 2 ans |
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Bart
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55f619efae
Initial commit with some empty Verilog template code from FPGC5
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il y a 2 ans |
