 bartpleiter
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9b3e3a5eb7
Initial progress with faster design.
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2 月之前 |
 bart
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207413dd90
Assembler only needs Int: function, fixed position of program lenght. Ported ROM and UART bootloader over from FPGC5. Updated documentation on interrupts. Added resets. Fixed bug in MU. Increased stack size. Tested everything in hardware. Probably some other fixes and things I forgot.
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2 年之前 |
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bart
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f5bc168700
Added DataMem to MU via Arbiter, fixed several bugs while doing this. Works with test code, but will most likely still contain bugs in certain cases.
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2 年之前 |
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bart
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6881f1be1d
Found bug where the next instruction after READ/WRITE is skipped if DataDelay but no InstrDelay
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2 年之前 |
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bart
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e8bc85adb6
Data memory now works with variable delays without breaking the pipeline
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2 年之前 |
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Bart
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302c69937e
Basic CPU design now done with afaik working hazard detection, forwarding and stalls. Tested in hardware on a EP4CE6 using two SSDisplays and dip switches to view the register content (and see if it matches the simulation). No interrupts yet as this can probably be done at a later stage.
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2 年之前 |
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Bart
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3714a90401
Forwarding now also works for data memory and also probably branches and other MEM operations. Fixed a bug in forwarding where EX was used instead of WB
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2 年之前 |
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Bart
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e5dd555fdb
Register forwarding now works for ALU operations, (memread getintid and savpc still needs forwarding). Regbank is simplified because no need for we_high anymore, load and loadhi are now done using an ALU operation.
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2 年之前 |
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Bart
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a76e895a39
Started working on the CPU pipeline. Basic load, arith and jumps seem to work now. No hazard handling yet.
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2 年之前 |
