 bartpleiter
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9438941e15
Initial setup to simulate 100mhz cpu in verilog testbench.
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6 月之前 |
 bart
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2fe0518bb3
Improved interrupt timing/alignment, fixing bug where interrupts are not allowed during the UART bootloader.
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1 年之前 |
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bart
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88681ec5d0
New arbiter that further improves performance by removing latency for instruction memory access. Created instability again, which I found to be caused by bad interrupt timings. Fixed by changing the interruptValid wire to use branch_MEM for alignment. I do not know why this fixed all problems as it is very hard to simulate this issue. L1 cache should be possible again!
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1 年之前 |
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bart
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add43b75da
L2 cache at 100MHz now greatly increases performance. Attempted to create l1i and l1d cache, but becomes unstable and the issue is difficult to similate/replicate. Therefore, all l1 cache is now bypassed and the code can be found in l1cacheUnstable.v. As no l1 cache anymore, I removed some ccache statements to increase performance as this instruction currently does nothing.
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1 年之前 |
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bart
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9a6bf3cd52
Improved reset for cache. Disabled l2 cache as it currently reduces performance. Added more CCache instructions to code, although likely not needed. Still instability issues when L1I cache is enabled.
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1 年之前 |
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bart
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7e81e7fa17
Added files missing from last commit (L1I cache).
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1 年之前 |
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bart
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dfb3bbb48e
Added L1D cache. Currently only works stable when valid bit is set 0 on WRITE. Valid bit 1 after cache miss read works fine for some reason.
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1 年之前 |
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bart
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28bcde6466
New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases.
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1 年之前 |
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bart
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9f74a9565f
Fixed more MU I/O bugs. Updated everything from BCC except the ASM to work on new CPU. Added back flasher programs. Fixed LOAD/HI bug by using unsigned const16 instead. Updated assembler including hotfix for FPGC jumping to addr3 after UART bootloader is done. FPGC6 now basically fully works again!
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2 年之前 |
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bart
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207413dd90
Assembler only needs Int: function, fixed position of program lenght. Ported ROM and UART bootloader over from FPGC5. Updated documentation on interrupts. Added resets. Fixed bug in MU. Increased stack size. Tested everything in hardware. Probably some other fixes and things I forgot.
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2 年之前 |
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bart
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69e83fb855
Fully implemented interrupts in verilog. Return address appears to work fine, but might need some further testing for different delays in the pipeline.
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2 年之前 |
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bart
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e493a27ab4
Started on interrupts. Triggering seems to work, reti still needs to be implemented
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2 年之前 |
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bart
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b74702c915
Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram
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2 年之前 |
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bart
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9662964536
Added back scripts for converting to spi.txt. Tested code to run from SPI flash, fixed cycle delay for SPI flash in output latch in MU which caused the bus_q to arrive a cycle later than bus_done.
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2 年之前 |
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bart
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f5bc168700
Added DataMem to MU via Arbiter, fixed several bugs while doing this. Works with test code, but will most likely still contain bugs in certain cases.
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2 年之前 |
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bart
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0e533922fb
Connected instruction memory to the MU via the arbiter
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2 年之前 |
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bart
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6881f1be1d
Found bug where the next instruction after READ/WRITE is skipped if DataDelay but no InstrDelay
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2 年之前 |
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bart
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e8bc85adb6
Data memory now works with variable delays without breaking the pipeline
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2 年之前 |
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Bart
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fb0e4b363f
Instruction memory can now have a delay without messing up the pipeline
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2 年之前 |
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Bart
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302c69937e
Basic CPU design now done with afaik working hazard detection, forwarding and stalls. Tested in hardware on a EP4CE6 using two SSDisplays and dip switches to view the register content (and see if it matches the simulation). No interrupts yet as this can probably be done at a later stage.
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2 年之前 |
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Bart
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3714a90401
Forwarding now also works for data memory and also probably branches and other MEM operations. Fixed a bug in forwarding where EX was used instead of WB
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2 年之前 |
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Bart
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e5dd555fdb
Register forwarding now works for ALU operations, (memread getintid and savpc still needs forwarding). Regbank is simplified because no need for we_high anymore, load and loadhi are now done using an ALU operation.
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2 年之前 |
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Bart
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9da01544e7
Jump flush now seems to work. Made simple Quartus project to test in hardware and it seems to work fine there as well
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2 年之前 |
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Bart
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a76e895a39
Started working on the CPU pipeline. Basic load, arith and jumps seem to work now. No hazard handling yet.
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2 年之前 |
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Bart
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55f619efae
Initial commit with some empty Verilog template code from FPGC5
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2 年之前 |
