 bart
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7e81e7fa17
Added files missing from last commit (L1I cache).
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1 年間 前 |
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bart
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207413dd90
Assembler only needs Int: function, fixed position of program lenght. Ported ROM and UART bootloader over from FPGC5. Updated documentation on interrupts. Added resets. Fixed bug in MU. Increased stack size. Tested everything in hardware. Probably some other fixes and things I forgot.
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2 年 前 |
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bart
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69e83fb855
Fully implemented interrupts in verilog. Return address appears to work fine, but might need some further testing for different delays in the pipeline.
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2 年 前 |
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bart
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e493a27ab4
Started on interrupts. Triggering seems to work, reti still needs to be implemented
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2 年 前 |
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bart
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ced78a8cbf
Fixed signed number bug in assembler, updated documentation about signed branches
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2 年 前 |
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bart
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1cf78e1fab
Added and updated the assembler (python version)
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2 年 前 |
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bart
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b74702c915
Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram
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2 年 前 |
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bart
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f5bc168700
Added DataMem to MU via Arbiter, fixed several bugs while doing this. Works with test code, but will most likely still contain bugs in certain cases.
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2 年 前 |
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bart
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0e533922fb
Connected instruction memory to the MU via the arbiter
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2 年 前 |
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bart
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916054063a
Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design
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2 年 前 |
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Bart
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43293f6ca4
Deleted some old memory files
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2 年 前 |
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Bart
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55f619efae
Initial commit with some empty Verilog template code from FPGC5
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2 年 前 |
