bart/FPGC6

Autore	SHA1 Messaggio	Data
bart	28bcde6466 New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases.	1 anno fa
bart	308cc6a90d Fixed SDRAM controller by setting phase shift to 180 degrees.	2 anni fa
bart	b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram	2 anni fa