Commit History

Autor SHA1 Mensaxe Data
  bartpleiter 9438941e15 Initial setup to simulate 100mhz cpu in verilog testbench. hai 6 meses
  bart 1026f4776c Cleaned up some files %!s(int64=2) %!d(string=hai) anos
  bart 1cf78e1fab Added and updated the assembler (python version) %!s(int64=2) %!d(string=hai) anos