 bart
|
01b9bb8f29
Added signed right shift operation to CPU, assembler, compiler, code and documentation.
|
2 gadi atpakaļ |
|
Bart
|
e5dd555fdb
Register forwarding now works for ALU operations, (memread getintid and savpc still needs forwarding). Regbank is simplified because no need for we_high anymore, load and loadhi are now done using an ALU operation.
|
2 gadi atpakaļ |
|
Bart
|
a76e895a39
Started working on the CPU pipeline. Basic load, arith and jumps seem to work now. No hazard handling yet.
|
2 gadi atpakaļ |
|
Bart
|
55f619efae
Initial commit with some empty Verilog template code from FPGC5
|
2 gadi atpakaļ |
