This website works better with JavaScript
Sākums
Izpētīt
Palīdzība
Pierakstīties
bart
/
FPGC6
spogulis no
https://github.com/bartpleiter/FPGC6
Vērot
1
Pievienot zvaigznīti
0
Atdalīts
0
Faili
Problēmas
0
Vikivietne
Koks:
8d56c91fea
Atzari
Tagi
EP4CE15
cpu100mhz
fast-cpu-pipeline
main
Revīziju vēsture
Meklēt
Autors
SHA1
Ziņojums
Datums
bart
9662964536
Added back scripts for converting to spi.txt. Tested code to run from SPI flash, fixed cycle delay for SPI flash in output latch in MU which caused the bus_q to arrive a cycle later than bus_done.
2 gadi atpakaļ
Bart
43293f6ca4
Deleted some old memory files
2 gadi atpakaļ
Bart
55f619efae
Initial commit with some empty Verilog template code from FPGC5
2 gadi atpakaļ