Commit History

Author SHA1 Message Date
  b4rt-dev 8d56c91fea Added fast (but inaccurate) and accurate (but slow) option for UART flasher. 2 years ago
  b4rt-dev 118fe8b319 Improved new button check in USB keyboard driver of BDOS 2 years ago
  b4rt-dev c4599a63cc New documentation structure. Updated some documentation. Added relevant graphics scripts and files from FPGC5 repo. 2 years ago
  bart 52b5107bba Created benchmarking tool which includes calculating digits of pi. 2 years ago
  bart d55077792f Updated BCC for B32P 2 years ago
  bart 6667e11cee Updated documentation on assembler and BDOS. 2 years ago
  bart 4c9ea8dbde Added list of things to add in documentation 2 years ago
  bart 1026f4776c Cleaned up some files 2 years ago
  bart b9bc26129d Added gitattributes to ignore the huge UARTbootloader.asm file. Deleted old quartus test project. 2 years ago
  bart 9f74a9565f Fixed more MU I/O bugs. Updated everything from BCC except the ASM to work on new CPU. Added back flasher programs. Fixed LOAD/HI bug by using unsigned const16 instead. Updated assembler including hotfix for FPGC jumping to addr3 after UART bootloader is done. FPGC6 now basically fully works again! 2 years ago
  bart 411c20ac98 Copied over BCC from FPGC5. No modifications yet. 2 years ago
  bart 58325c3b1d Added Subl3 build files 2 years ago
  bart 207413dd90 Assembler only needs Int: function, fixed position of program lenght. Ported ROM and UART bootloader over from FPGC5. Updated documentation on interrupts. Added resets. Fixed bug in MU. Increased stack size. Tested everything in hardware. Probably some other fixes and things I forgot. 2 years ago
  bart 69e83fb855 Fully implemented interrupts in verilog. Return address appears to work fine, but might need some further testing for different delays in the pipeline. 2 years ago
  bart e493a27ab4 Started on interrupts. Triggering seems to work, reti still needs to be implemented 2 years ago
  bart ced78a8cbf Fixed signed number bug in assembler, updated documentation about signed branches 2 years ago
  bart 1cf78e1fab Added and updated the assembler (python version) 2 years ago
  bart e2ec5415ce Documentation update 2 years ago
  bart baff95d710 Regbank and stack are now placed in BRAM, fixed combinational loop but further testing needed. 2 years ago
  bart b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram 2 years ago
  bart 9662964536 Added back scripts for converting to spi.txt. Tested code to run from SPI flash, fixed cycle delay for SPI flash in output latch in MU which caused the bus_q to arrive a cycle later than bus_done. 2 years ago
  bart f5bc168700 Added DataMem to MU via Arbiter, fixed several bugs while doing this. Works with test code, but will most likely still contain bugs in certain cases. 2 years ago
  bart 0e533922fb Connected instruction memory to the MU via the arbiter 2 years ago
  bart 916054063a Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design 2 years ago
  bart 6881f1be1d Found bug where the next instruction after READ/WRITE is skipped if DataDelay but no InstrDelay 2 years ago
  bart e8bc85adb6 Data memory now works with variable delays without breaking the pipeline 2 years ago
  Bart fb0e4b363f Instruction memory can now have a delay without messing up the pipeline 2 years ago
  Bart 3d9b4194f7 Added initial documentation 2 years ago
  Bart 302c69937e Basic CPU design now done with afaik working hazard detection, forwarding and stalls. Tested in hardware on a EP4CE6 using two SSDisplays and dip switches to view the register content (and see if it matches the simulation). No interrupts yet as this can probably be done at a later stage. 2 years ago
  Bart 9ec3298860 Updated README and added licence so repo can go public now 2 years ago