 bart
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916054063a
Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design
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2 years ago |
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bart
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6881f1be1d
Found bug where the next instruction after READ/WRITE is skipped if DataDelay but no InstrDelay
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2 years ago |
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bart
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e8bc85adb6
Data memory now works with variable delays without breaking the pipeline
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2 years ago |
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Bart
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fb0e4b363f
Instruction memory can now have a delay without messing up the pipeline
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2 years ago |
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Bart
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3d9b4194f7
Added initial documentation
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2 years ago |
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Bart
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302c69937e
Basic CPU design now done with afaik working hazard detection, forwarding and stalls. Tested in hardware on a EP4CE6 using two SSDisplays and dip switches to view the register content (and see if it matches the simulation). No interrupts yet as this can probably be done at a later stage.
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2 years ago |
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Bart
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9ec3298860
Updated README and added licence so repo can go public now
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2 years ago |
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Bart
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3714a90401
Forwarding now also works for data memory and also probably branches and other MEM operations. Fixed a bug in forwarding where EX was used instead of WB
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2 years ago |
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Bart
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e5dd555fdb
Register forwarding now works for ALU operations, (memread getintid and savpc still needs forwarding). Regbank is simplified because no need for we_high anymore, load and loadhi are now done using an ALU operation.
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2 years ago |
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Bart
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9da01544e7
Jump flush now seems to work. Made simple Quartus project to test in hardware and it seems to work fine there as well
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2 years ago |
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Bart
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a76e895a39
Started working on the CPU pipeline. Basic load, arith and jumps seem to work now. No hazard handling yet.
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2 years ago |
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Bart
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7b0a44b7be
Added testbench template with gtkw config
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2 years ago |
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Bart
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43293f6ca4
Deleted some old memory files
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2 years ago |
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Bart
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55f619efae
Initial commit with some empty Verilog template code from FPGC5
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2 years ago |
