 bart
|
82a433530c
Reverted L2 cache size to 1024 words for easier debugging.
|
1 год назад |
|
bart
|
da2bff2ea2
Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking.
|
1 год назад |
|
bart
|
2287e54c6b
Integrated valid bits into cache block ram. Reset now iteratively clears the entire cache. Allows for much lower FPGA usage and better timings. Should be able to greatly increase cache size as there is an abundance of BRAM.
|
1 год назад |
|
bart
|
2fe0518bb3
Improved interrupt timing/alignment, fixing bug where interrupts are not allowed during the UART bootloader.
|
1 год назад |
|
bart
|
52f2819774
Removed leftover ccache instructions from debugging instability problems. Commented out required ccache instructions for when L1I cache returns in the future.
|
1 год назад |
|
bart
|
9a285550c0
Updated documentation a bit, added newlines to BENCH, removed wrong comments from L2cache.v
|
1 год назад |
|
bart
|
88681ec5d0
New arbiter that further improves performance by removing latency for instruction memory access. Created instability again, which I found to be caused by bad interrupt timings. Fixed by changing the interruptValid wire to use branch_MEM for alignment. I do not know why this fixed all problems as it is very hard to simulate this issue. L1 cache should be possible again!
|
1 год назад |
|
bart
|
add43b75da
L2 cache at 100MHz now greatly increases performance. Attempted to create l1i and l1d cache, but becomes unstable and the issue is difficult to similate/replicate. Therefore, all l1 cache is now bypassed and the code can be found in l1cacheUnstable.v. As no l1 cache anymore, I removed some ccache statements to increase performance as this instruction currently does nothing.
|
1 год назад |
|
bart
|
5af536210d
Fixed instability by adding clear cache instruction during SPI transfer. No idea why this fixed the issue, as the I/O address range is above the limit for cache to work.
|
1 год назад |
|
bart
|
9a6bf3cd52
Improved reset for cache. Disabled l2 cache as it currently reduces performance. Added more CCache instructions to code, although likely not needed. Still instability issues when L1I cache is enabled.
|
1 год назад |
|
bart
|
7e81e7fa17
Added files missing from last commit (L1I cache).
|
1 год назад |
|
bart
|
3253b1bc2c
Added L1I cache. Added clear cache instruction, which is now added in the UART bootloader and BDOS program loaders. Fixed too fast read part in SPI flasher. Snake userbdos program now sometimes crashes, which needs further investigation.
|
1 год назад |
|
bart
|
dfb3bbb48e
Added L1D cache. Currently only works stable when valid bit is set 0 on WRITE. Valid bit 1 after cache miss read works fine for some reason.
|
1 год назад |
|
bart
|
b6831c4209
Added L2 cache (no L1 for now) between CPU and SDRAM controller. No noticable performance difference, can likely be optimized further to reduce cache hit latency.
|
1 год назад |
|
bart
|
28bcde6466
New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases.
|
1 год назад |
|
bart
|
240770cb51
Progress on asm for bcc with new architecture. Started on SDRAM testbench for new controller.
|
1 год назад |
|
bart
|
1a2f5e6c55
Added qws Quartus file.
|
1 год назад |
|
bart
|
e1bb01a621
Cleaned and renamed Quartus project.
|
1 год назад |
|
bart
|
d602419429
Added support for negative ints in .dw for python assembler.
|
1 год назад |
|
bart
|
7e822dcae0
Made assembly for rendering mandelbrot program, with other improvements as well.
|
2 лет назад |
|
bart
|
19b70deac8
Added support for signed .dw instructions.
|
2 лет назад |
 Bart
|
cf2db3b9cd
Merge pull request #1 from b4rt-dev/PixelEngine
|
2 лет назад |
|
bart
|
01b9bb8f29
Added signed right shift operation to CPU, assembler, compiler, code and documentation.
|
2 лет назад |
|
bart
|
4dd2ff7765
Merged from main.
|
2 лет назад |
|
bart
|
6e3cd7cd9c
PixelEngine now works in hardware with both HDMI and NTSC. Added pxtest and mandelbrot test programs.
|
2 лет назад |
|
bart
|
7b14d2d273
Improved Pixel Engine.
|
2 лет назад |
|
bart
|
6dc8fc396f
Added Pixel Engine in simulation.
|
2 лет назад |
|
bart
|
442d51ba85
Added images to documentation, HDMI is working without lvds, init of new sdram controller done.
|
2 лет назад |
|
bart
|
308cc6a90d
Fixed SDRAM controller by setting phase shift to 180 degrees.
|
2 лет назад |
|
bart
|
a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
|
2 лет назад |
