 bart
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b6831c4209
Added L2 cache (no L1 for now) between CPU and SDRAM controller. No noticable performance difference, can likely be optimized further to reduce cache hit latency.
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1 anno fa |
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bart
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69e83fb855
Fully implemented interrupts in verilog. Return address appears to work fine, but might need some further testing for different delays in the pipeline.
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2 anni fa |
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bart
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e493a27ab4
Started on interrupts. Triggering seems to work, reti still needs to be implemented
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2 anni fa |
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bart
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9662964536
Added back scripts for converting to spi.txt. Tested code to run from SPI flash, fixed cycle delay for SPI flash in output latch in MU which caused the bus_q to arrive a cycle later than bus_done.
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2 anni fa |
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bart
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0e533922fb
Connected instruction memory to the MU via the arbiter
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2 anni fa |
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bart
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916054063a
Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design
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2 anni fa |
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Bart
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fb0e4b363f
Instruction memory can now have a delay without messing up the pipeline
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2 anni fa |
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Bart
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3714a90401
Forwarding now also works for data memory and also probably branches and other MEM operations. Fixed a bug in forwarding where EX was used instead of WB
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2 anni fa |
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Bart
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9da01544e7
Jump flush now seems to work. Made simple Quartus project to test in hardware and it seems to work fine there as well
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2 anni fa |
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Bart
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a76e895a39
Started working on the CPU pipeline. Basic load, arith and jumps seem to work now. No hazard handling yet.
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2 anni fa |
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Bart
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7b0a44b7be
Added testbench template with gtkw config
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2 anni fa |
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Bart
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55f619efae
Initial commit with some empty Verilog template code from FPGC5
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2 anni fa |
