 bart
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7e81e7fa17
Added files missing from last commit (L1I cache).
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1 年間 前 |
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bart
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69e83fb855
Fully implemented interrupts in verilog. Return address appears to work fine, but might need some further testing for different delays in the pipeline.
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2 年 前 |
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Bart
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e5dd555fdb
Register forwarding now works for ALU operations, (memread getintid and savpc still needs forwarding). Regbank is simplified because no need for we_high anymore, load and loadhi are now done using an ALU operation.
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2 年 前 |
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Bart
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9da01544e7
Jump flush now seems to work. Made simple Quartus project to test in hardware and it seems to work fine there as well
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2 年 前 |
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Bart
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a76e895a39
Started working on the CPU pipeline. Basic load, arith and jumps seem to work now. No hazard handling yet.
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2 年 前 |
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Bart
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55f619efae
Initial commit with some empty Verilog template code from FPGC5
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2 年 前 |
