 Bart
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3d9b4194f7
Added initial documentation
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2 年之前 |
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Bart
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302c69937e
Basic CPU design now done with afaik working hazard detection, forwarding and stalls. Tested in hardware on a EP4CE6 using two SSDisplays and dip switches to view the register content (and see if it matches the simulation). No interrupts yet as this can probably be done at a later stage.
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2 年之前 |
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Bart
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9ec3298860
Updated README and added licence so repo can go public now
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2 年之前 |
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Bart
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9da01544e7
Jump flush now seems to work. Made simple Quartus project to test in hardware and it seems to work fine there as well
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2 年之前 |
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Bart
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a76e895a39
Started working on the CPU pipeline. Basic load, arith and jumps seem to work now. No hazard handling yet.
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2 年之前 |
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Bart
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55f619efae
Initial commit with some empty Verilog template code from FPGC5
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2 年之前 |
