bart/FPGC6

mirror da https://github.com/bartpleiter/FPGC6

Autore	SHA1 Messaggio	Data
bart	e1bb01a621 Cleaned and renamed Quartus project.	1 anno fa
bart	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	2 anni fa
bart	b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram	2 anni fa