 bart
|
6b31f51206
Added file and dir creation to BRFS.
|
7 месяцев назад |
|
bart
|
b6831c4209
Added L2 cache (no L1 for now) between CPU and SDRAM controller. No noticable performance difference, can likely be optimized further to reduce cache hit latency.
|
1 год назад |
|
bart
|
01b9bb8f29
Added signed right shift operation to CPU, assembler, compiler, code and documentation.
|
1 год назад |
|
b4rt-dev
|
8d56c91fea
Added fast (but inaccurate) and accurate (but slow) option for UART flasher.
|
2 лет назад |
|
bart
|
9f74a9565f
Fixed more MU I/O bugs. Updated everything from BCC except the ASM to work on new CPU. Added back flasher programs. Fixed LOAD/HI bug by using unsigned const16 instead. Updated assembler including hotfix for FPGC jumping to addr3 after UART bootloader is done. FPGC6 now basically fully works again!
|
2 лет назад |
