bart/FPGC6

tükrözi: https://github.com/bartpleiter/FPGC6

Szerző	SHA1 Üzenet	Dátum
bart	b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram	2 éve
Bart	43293f6ca4 Deleted some old memory files	2 éve
Bart	55f619efae Initial commit with some empty Verilog template code from FPGC5	2 éve