 bart
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7e81e7fa17
Added files missing from last commit (L1I cache).
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1 year ago |
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bart
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3253b1bc2c
Added L1I cache. Added clear cache instruction, which is now added in the UART bootloader and BDOS program loaders. Fixed too fast read part in SPI flasher. Snake userbdos program now sometimes crashes, which needs further investigation.
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1 year ago |
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bart
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dfb3bbb48e
Added L1D cache. Currently only works stable when valid bit is set 0 on WRITE. Valid bit 1 after cache miss read works fine for some reason.
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1 year ago |
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bart
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b6831c4209
Added L2 cache (no L1 for now) between CPU and SDRAM controller. No noticable performance difference, can likely be optimized further to reduce cache hit latency.
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1 year ago |
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bart
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28bcde6466
New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases.
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1 year ago |
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bart
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240770cb51
Progress on asm for bcc with new architecture. Started on SDRAM testbench for new controller.
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1 year ago |
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bart
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1a2f5e6c55
Added qws Quartus file.
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1 year ago |
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bart
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e1bb01a621
Cleaned and renamed Quartus project.
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1 year ago |
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bart
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d602419429
Added support for negative ints in .dw for python assembler.
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1 year ago |
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bart
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7e822dcae0
Made assembly for rendering mandelbrot program, with other improvements as well.
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2 years ago |
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bart
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19b70deac8
Added support for signed .dw instructions.
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2 years ago |
 Bart
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cf2db3b9cd
Merge pull request #1 from b4rt-dev/PixelEngine
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2 years ago |
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bart
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01b9bb8f29
Added signed right shift operation to CPU, assembler, compiler, code and documentation.
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2 years ago |
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bart
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4dd2ff7765
Merged from main.
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2 years ago |
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bart
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6e3cd7cd9c
PixelEngine now works in hardware with both HDMI and NTSC. Added pxtest and mandelbrot test programs.
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2 years ago |
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bart
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7b14d2d273
Improved Pixel Engine.
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2 years ago |
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bart
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6dc8fc396f
Added Pixel Engine in simulation.
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2 years ago |
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bart
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442d51ba85
Added images to documentation, HDMI is working without lvds, init of new sdram controller done.
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2 years ago |
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bart
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308cc6a90d
Fixed SDRAM controller by setting phase shift to 180 degrees.
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2 years ago |
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bart
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 years ago |
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b4rt-dev
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8d56c91fea
Added fast (but inaccurate) and accurate (but slow) option for UART flasher.
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2 years ago |
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b4rt-dev
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118fe8b319
Improved new button check in USB keyboard driver of BDOS
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2 years ago |
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b4rt-dev
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c4599a63cc
New documentation structure. Updated some documentation. Added relevant graphics scripts and files from FPGC5 repo.
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2 years ago |
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bart
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52b5107bba
Created benchmarking tool which includes calculating digits of pi.
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2 years ago |
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bart
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d55077792f
Updated BCC for B32P
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2 years ago |
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bart
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6667e11cee
Updated documentation on assembler and BDOS.
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2 years ago |
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bart
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4c9ea8dbde
Added list of things to add in documentation
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2 years ago |
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bart
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1026f4776c
Cleaned up some files
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2 years ago |
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bart
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b9bc26129d
Added gitattributes to ignore the huge UARTbootloader.asm file. Deleted old quartus test project.
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2 years ago |
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bart
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9f74a9565f
Fixed more MU I/O bugs. Updated everything from BCC except the ASM to work on new CPU. Added back flasher programs. Fixed LOAD/HI bug by using unsigned const16 instead. Updated assembler including hotfix for FPGC jumping to addr3 after UART bootloader is done. FPGC6 now basically fully works again!
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2 years ago |
