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bart
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FPGC6
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https://github.com/bartpleiter/FPGC6
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Struktur:
33d828b6b9
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EP4CE15
cpu100mhz
fast-cpu-pipeline
main
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bart
7b14d2d273
Improved Pixel Engine.
vor 2 Jahren
bart
1026f4776c
Cleaned up some files
vor 2 Jahren
bart
b74702c915
Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram
vor 2 Jahren