bart/FPGC6

zrkadlo https://github.com/bartpleiter/FPGC6

Autor	SHA1 Správa	Dátum
bart	e1bb01a621 Cleaned and renamed Quartus project.	2 rokov pred
bart	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	2 rokov pred
bart	b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram	2 rokov pred