bart/FPGC6

réplica de https://github.com/bartpleiter/FPGC6

Autor	SHA1 Mensaxe	Data
bart	308cc6a90d Fixed SDRAM controller by setting phase shift to 180 degrees.	%!s(int64=2) %!d(string=hai) anos
bart	a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.	%!s(int64=2) %!d(string=hai) anos
bart	b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram	%!s(int64=2) %!d(string=hai) anos