add43b75daL2 cache at 100MHz now greatly increases performance. Attempted to create l1i and l1d cache, but becomes unstable and the issue is difficult to similate/replicate. Therefore, all l1 cache is now bypassed and the code can be found in l1cacheUnstable.v. As no l1 cache anymore, I removed some ccache statements to increase performance as this instruction currently does nothing.
1 年之前
bart
b6831c4209Added L2 cache (no L1 for now) between CPU and SDRAM controller. No noticable performance difference, can likely be optimized further to reduce cache hit latency.
bart