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bart
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FPGC6
mirror of https://github.com/bartpleiter/FPGC6
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Commit History

Author SHA1 Message Date
  bart b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram 2 years ago
  Bart 43293f6ca4 Deleted some old memory files 2 years ago
  Bart 55f619efae Initial commit with some empty Verilog template code from FPGC5 2 years ago