 bart
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da7bf6bf21
Added script for uploading text file. Updated syncCfiles script.
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7 mesi fa |
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bart
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6b31f51206
Added file and dir creation to BRFS.
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7 mesi fa |
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bart
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 anni fa |
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bart
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207413dd90
Assembler only needs Int: function, fixed position of program lenght. Ported ROM and UART bootloader over from FPGC5. Updated documentation on interrupts. Added resets. Fixed bug in MU. Increased stack size. Tested everything in hardware. Probably some other fixes and things I forgot.
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2 anni fa |
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Bart
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9da01544e7
Jump flush now seems to work. Made simple Quartus project to test in hardware and it seems to work fine there as well
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2 anni fa |
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Bart
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55f619efae
Initial commit with some empty Verilog template code from FPGC5
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2 anni fa |
