 bart
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b6831c4209
Added L2 cache (no L1 for now) between CPU and SDRAM controller. No noticable performance difference, can likely be optimized further to reduce cache hit latency.
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il y a 1 an |
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bart
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01b9bb8f29
Added signed right shift operation to CPU, assembler, compiler, code and documentation.
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il y a 2 ans |
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b4rt-dev
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8d56c91fea
Added fast (but inaccurate) and accurate (but slow) option for UART flasher.
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il y a 2 ans |
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bart
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9f74a9565f
Fixed more MU I/O bugs. Updated everything from BCC except the ASM to work on new CPU. Added back flasher programs. Fixed LOAD/HI bug by using unsigned const16 instead. Updated assembler including hotfix for FPGC jumping to addr3 after UART bootloader is done. FPGC6 now basically fully works again!
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il y a 2 ans |
