Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking.

Quartus/FPGC.qsf

@@ -223,13 +223,13 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to GPI[0]
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to GPI[1]
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to GPI[2]
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to GPI[3]
+set_global_assignment -name OPTIMIZATION_MODE BALANCED
 set_global_assignment -name SDC_FILE FPGC.sdc
 set_global_assignment -name QIP_FILE clkMux/synthesis/clkMux.qip
 set_global_assignment -name VERILOG_FILE modules/FPGC.v
 set_global_assignment -name VERILOG_FILE modules/Memory/L1Icache.v
 set_global_assignment -name VERILOG_FILE modules/Memory/L1Dcache.v
 set_global_assignment -name VERILOG_FILE modules/Memory/L2cache.v
-set_global_assignment -name VERILOG_FILE Source/Test02_project_key.v
 set_global_assignment -name VERILOG_FILE modules/GPU/NTSC/RGBtoYPhaseAmpl.v
 set_global_assignment -name VERILOG_FILE modules/GPU/NTSC/RGB332toNTSC.v
 set_global_assignment -name VERILOG_FILE modules/GPU/NTSC/PhaseGen.v

Quartus/NTSC_pll.ppf

@@ -4,8 +4,6 @@
 <global>
 <pin name="areset" direction="input" scope="external"  />
 <pin name="inclk0" direction="input" scope="external" source="clock"  />
-<pin name="c0" direction="output" scope="external" source="clock"  />
-<pin name="c1" direction="output" scope="external" source="clock"  />
 <pin name="c2" direction="output" scope="external" source="clock"  />
 <pin name="c3" direction="output" scope="external" source="clock"  />
 

Quartus/NTSC_pll.v

@@ -40,15 +40,11 @@
 module NTSC_pll (
 	areset,
 	inclk0,
-	c0,
-	c1,
 	c2,
 	c3);
 
 	input	  areset;
 	input	  inclk0;
-	output	  c0;
-	output	  c1;
 	output	  c2;
 	output	  c3;
 `ifndef ALTERA_RESERVED_QIS
@@ -60,21 +56,17 @@ module NTSC_pll (
 `endif
 
 	wire [4:0] sub_wire0;
-	wire [0:0] sub_wire7 = 1'h0;
-	wire [3:3] sub_wire4 = sub_wire0[3:3];
-	wire [2:2] sub_wire3 = sub_wire0[2:2];
-	wire [1:1] sub_wire2 = sub_wire0[1:1];
-	wire [0:0] sub_wire1 = sub_wire0[0:0];
-	wire  c0 = sub_wire1;
-	wire  c1 = sub_wire2;
-	wire  c2 = sub_wire3;
-	wire  c3 = sub_wire4;
-	wire  sub_wire5 = inclk0;
-	wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
+	wire [0:0] sub_wire5 = 1'h0;
+	wire [3:3] sub_wire2 = sub_wire0[3:3];
+	wire [2:2] sub_wire1 = sub_wire0[2:2];
+	wire  c2 = sub_wire1;
+	wire  c3 = sub_wire2;
+	wire  sub_wire3 = inclk0;
+	wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
 
 	altpll	altpll_component (
 				.areset (areset),
-				.inclk (sub_wire6),
+				.inclk (sub_wire4),
 				.clk (sub_wire0),
 				.activeclock (),
 				.clkbad (),
@@ -112,14 +104,6 @@ module NTSC_pll (
 				.vcounderrange ());
 	defparam
 		altpll_component.bandwidth_type = "AUTO",
-		altpll_component.clk0_divide_by = 220,
-		altpll_component.clk0_duty_cycle = 50,
-		altpll_component.clk0_multiply_by = 63,
-		altpll_component.clk0_phase_shift = "0",
-		altpll_component.clk1_divide_by = 55,
-		altpll_component.clk1_duty_cycle = 50,
-		altpll_component.clk1_multiply_by = 126,
-		altpll_component.clk1_phase_shift = "0",
 		altpll_component.clk2_divide_by = 125,
 		altpll_component.clk2_duty_cycle = 50,
 		altpll_component.clk2_multiply_by = 63,
@@ -128,7 +112,7 @@ module NTSC_pll (
 		altpll_component.clk3_duty_cycle = 50,
 		altpll_component.clk3_multiply_by = 63,
 		altpll_component.clk3_phase_shift = "0",
-		altpll_component.compensate_clock = "CLK0",
+		altpll_component.compensate_clock = "CLK2",
 		altpll_component.inclk0_input_frequency = 20000,
 		altpll_component.intended_device_family = "Cyclone IV E",
 		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=NTSC_pll",
@@ -160,8 +144,8 @@ module NTSC_pll (
 		altpll_component.port_scandone = "PORT_UNUSED",
 		altpll_component.port_scanread = "PORT_UNUSED",
 		altpll_component.port_scanwrite = "PORT_UNUSED",
-		altpll_component.port_clk0 = "PORT_USED",
-		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk0 = "PORT_UNUSED",
+		altpll_component.port_clk1 = "PORT_UNUSED",
 		altpll_component.port_clk2 = "PORT_USED",
 		altpll_component.port_clk3 = "PORT_USED",
 		altpll_component.port_clk4 = "PORT_UNUSED",
@@ -197,19 +181,13 @@ endmodule
 // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
 // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
 // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c2"
 // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "220"
-// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "55"
 // Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "125"
 // Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
-// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
 // Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "14.318182"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "114.545456"
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.200001"
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "126.000000"
 // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
@@ -231,41 +209,25 @@ endmodule
 // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
 // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
 // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
 // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 // Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
 // Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "63"
-// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "126"
 // Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "63"
 // Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
 // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "126.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
 // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
@@ -289,33 +251,19 @@ endmodule
 // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000"
 // Retrieval info: PRIVATE: SPREAD_USE STRING "0"
 // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
 // Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
 // Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
 // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
 // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
 // Retrieval info: PRIVATE: USE_CLK2 STRING "1"
 // Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
 // Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
 // Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
 // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
 // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "220"
-// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "63"
-// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "55"
-// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "126"
-// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 // Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "125"
 // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
 // Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "63"
@@ -324,7 +272,7 @@ endmodule
 // Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
 // Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "63"
 // Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK2"
 // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
 // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
@@ -355,8 +303,8 @@ endmodule
 // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
@@ -374,16 +322,12 @@ endmodule
 // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
 // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
 // Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
 // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
 // Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
 // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
 // Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
 // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
 // Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
 // Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
 // Retrieval info: GEN_FILE: TYPE_NORMAL NTSC_pll.v TRUE

Quartus/NTSC_pll_bb.v

@@ -35,15 +35,11 @@
 module NTSC_pll (
 	areset,
 	inclk0,
-	c0,
-	c1,
 	c2,
 	c3);
 
 	input	  areset;
 	input	  inclk0;
-	output	  c0;
-	output	  c1;
 	output	  c2;
 	output	  c3;
 `ifndef ALTERA_RESERVED_QIS
@@ -72,19 +68,13 @@ endmodule
 // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
 // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
 // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c2"
 // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "220"
-// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "55"
 // Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "125"
 // Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
-// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
 // Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "14.318182"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "114.545456"
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.200001"
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "126.000000"
 // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
@@ -106,41 +96,25 @@ endmodule
 // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
 // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
 // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
 // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 // Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
 // Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "63"
-// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "126"
 // Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "63"
 // Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
 // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "126.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
 // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
@@ -164,33 +138,19 @@ endmodule
 // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000"
 // Retrieval info: PRIVATE: SPREAD_USE STRING "0"
 // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
 // Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
 // Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
 // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
 // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
 // Retrieval info: PRIVATE: USE_CLK2 STRING "1"
 // Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
 // Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
 // Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
 // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
 // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "220"
-// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "63"
-// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "55"
-// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "126"
-// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 // Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "125"
 // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
 // Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "63"
@@ -199,7 +159,7 @@ endmodule
 // Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
 // Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "63"
 // Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK2"
 // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
 // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
@@ -230,8 +190,8 @@ endmodule
 // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
@@ -249,16 +209,12 @@ endmodule
 // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
 // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
 // Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
 // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
 // Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
 // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
 // Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
 // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
 // Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
 // Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
 // Retrieval info: GEN_FILE: TYPE_NORMAL NTSC_pll.v TRUE

Quartus/clock_pll.ppf

@@ -7,6 +7,8 @@
 <pin name="c0" direction="output" scope="external" source="clock"  />
 <pin name="c1" direction="output" scope="external" source="clock"  />
 <pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="c3" direction="output" scope="external" source="clock"  />
+<pin name="c4" direction="output" scope="external" source="clock"  />
 
 </global>
 </pinplan>

Quartus/clock_pll.v

@@ -42,13 +42,17 @@ module clock_pll (
 	inclk0,
 	c0,
 	c1,
-	c2);
+	c2,
+	c3,
+	c4);
 
 	input	  areset;
 	input	  inclk0;
 	output	  c0;
 	output	  c1;
 	output	  c2;
+	output	  c3;
+	output	  c4;
 `ifndef ALTERA_RESERVED_QIS
 // synopsys translate_off
 `endif
@@ -58,19 +62,23 @@ module clock_pll (
 `endif
 
 	wire [4:0] sub_wire0;
-	wire [0:0] sub_wire6 = 1'h0;
+	wire [0:0] sub_wire8 = 1'h0;
+	wire [4:4] sub_wire5 = sub_wire0[4:4];
+	wire [3:3] sub_wire4 = sub_wire0[3:3];
 	wire [2:2] sub_wire3 = sub_wire0[2:2];
 	wire [1:1] sub_wire2 = sub_wire0[1:1];
 	wire [0:0] sub_wire1 = sub_wire0[0:0];
 	wire  c0 = sub_wire1;
 	wire  c1 = sub_wire2;
 	wire  c2 = sub_wire3;
-	wire  sub_wire4 = inclk0;
-	wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
+	wire  c3 = sub_wire4;
+	wire  c4 = sub_wire5;
+	wire  sub_wire6 = inclk0;
+	wire [1:0] sub_wire7 = {sub_wire8, sub_wire6};
 
 	altpll	altpll_component (
 				.areset (areset),
-				.inclk (sub_wire5),
+				.inclk (sub_wire7),
 				.clk (sub_wire0),
 				.activeclock (),
 				.clkbad (),
@@ -120,6 +128,14 @@ module clock_pll (
 		altpll_component.clk2_duty_cycle = 50,
 		altpll_component.clk2_multiply_by = 1,
 		altpll_component.clk2_phase_shift = "0",
+		altpll_component.clk3_divide_by = 2,
+		altpll_component.clk3_duty_cycle = 50,
+		altpll_component.clk3_multiply_by = 1,
+		altpll_component.clk3_phase_shift = "0",
+		altpll_component.clk4_divide_by = 2,
+		altpll_component.clk4_duty_cycle = 50,
+		altpll_component.clk4_multiply_by = 5,
+		altpll_component.clk4_phase_shift = "0",
 		altpll_component.compensate_clock = "CLK0",
 		altpll_component.inclk0_input_frequency = 20000,
 		altpll_component.intended_device_family = "Cyclone IV E",
@@ -155,8 +171,8 @@ module clock_pll (
 		altpll_component.port_clk0 = "PORT_USED",
 		altpll_component.port_clk1 = "PORT_USED",
 		altpll_component.port_clk2 = "PORT_USED",
-		altpll_component.port_clk3 = "PORT_UNUSED",
-		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_USED",
+		altpll_component.port_clk4 = "PORT_USED",
 		altpll_component.port_clk5 = "PORT_UNUSED",
 		altpll_component.port_clkena0 = "PORT_UNUSED",
 		altpll_component.port_clkena1 = "PORT_UNUSED",
@@ -195,12 +211,18 @@ endmodule
 // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
 // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
 // Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
 // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "50.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "25.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "125.000000"
 // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -223,32 +245,48 @@ endmodule
 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
 // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
 // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
 // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 // Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
 // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
 // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
 // Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "1"
 // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
 // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "50.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "25.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "125.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
 // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "180.00000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps"
 // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
 // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -273,15 +311,21 @@ endmodule
 // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
 // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
 // Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
 // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
 // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 // Retrieval info: PRIVATE: USE_CLK0 STRING "1"
 // Retrieval info: PRIVATE: USE_CLK1 STRING "1"
 // Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
 // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
 // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
 // Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
 // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
 // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
@@ -298,6 +342,14 @@ endmodule
 // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
 // Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
 // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
 // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
@@ -332,8 +384,8 @@ endmodule
 // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
@@ -351,6 +403,8 @@ endmodule
 // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
 // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
 // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
 // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
 // Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
 // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
@@ -358,6 +412,8 @@ endmodule
 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
 // Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
 // Retrieval info: GEN_FILE: TYPE_NORMAL clock_pll.v TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL clock_pll.ppf TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL clock_pll.inc FALSE

Quartus/clock_pll_bb.v

@@ -37,13 +37,17 @@ module clock_pll (
 	inclk0,
 	c0,
 	c1,
-	c2);
+	c2,
+	c3,
+	c4);
 
 	input	  areset;
 	input	  inclk0;
 	output	  c0;
 	output	  c1;
 	output	  c2;
+	output	  c3;
+	output	  c4;
 `ifndef ALTERA_RESERVED_QIS
 // synopsys translate_off
 `endif
@@ -76,12 +80,18 @@ endmodule
 // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
 // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
 // Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
 // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "50.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "25.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "125.000000"
 // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -104,32 +114,48 @@ endmodule
 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
 // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
 // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
 // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 // Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
 // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
 // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
 // Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "1"
 // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
 // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "50.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "25.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "125.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
 // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "180.00000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps"
 // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
 // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -154,15 +180,21 @@ endmodule
 // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
 // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
 // Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
 // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
 // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 // Retrieval info: PRIVATE: USE_CLK0 STRING "1"
 // Retrieval info: PRIVATE: USE_CLK1 STRING "1"
 // Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
 // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
 // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
 // Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
 // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
 // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
@@ -179,6 +211,14 @@ endmodule
 // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
 // Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
 // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
 // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
@@ -213,8 +253,8 @@ endmodule
 // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
@@ -232,6 +272,8 @@ endmodule
 // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
 // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
 // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
 // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
 // Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
 // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
@@ -239,6 +281,8 @@ endmodule
 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
 // Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
 // Retrieval info: GEN_FILE: TYPE_NORMAL clock_pll.v TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL clock_pll.ppf TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL clock_pll.inc FALSE

Quartus/modules/FPGC.v

@@ -124,7 +124,9 @@ clock_pll clkPll(
 .areset (1'b0),
 .c0     (clk_SDRAM),
 .c1     (SDRAM_CLK),
-.c2     (clk)
+.c2     (clk),
+.c3     (clkPixel),
+.c4     (clkTMDShalf)
 );
 
 wire clk14; //14.31818MHz (50*63/220)
@@ -138,18 +140,21 @@ wire clk114; //14.31818 * 8 MHz = 114.5454MHz (50*(63*2)/55)
 //.outclk_3     (clkTMDShalf)
 //);
 
+/*
 NTSC_pll ntscPll(
 .inclk0 (clk),
 .areset (1'b0),
-.c0     (clk14),
-.c1     (clk114),
+//.c0     (clk14),
+//.c1     (clk114),
 .c2     (clkPixel), // 25.2MHz dirty fix to allow ALTCLKBUF
 .c3     (clkTMDShalf)
 );
+*/
 
 wire clkMuxOut;
-wire selectOutput;    // 1 -> HDMI, 0 -> Composite
+//wire selectOutput;    // 1 -> HDMI, 0 -> Composite
 
+/*
 clkMux clkmux(
 .inclk0x(clock),
 .inclk1x(clock),
@@ -158,6 +163,8 @@ clkMux clkmux(
 .clkselect({1'b1, selectOutput}),
 .outclk(clkMuxOut)
 );
+*/
+assign clkMuxOut = clkPixel;
 
 //--------------------Reset&Stabilizers-----------------------
 // Reset signals
@@ -191,9 +198,9 @@ MultiStabilizer multistabilizer(
 .u6     (frameDrawn),
 .s6     (frameDrawn_stable),
 .u7     (DIPS[0]),
-.s7     (boot_mode_stable),
-.u8     (DIPS[1]),
-.s8     (selectOutput)
+.s7     (boot_mode_stable)
+//.u8     (DIPS[1]),
+//.s8     (selectOutput)
 );
 
 //assign selectOutput = 1'b0;
@@ -473,8 +480,8 @@ FSX fsx(
 // Clocks
 .clkPixel       (clkPixel),
 .clkTMDShalf    (clkTMDShalf),
-.clk14          (clk14),
-.clk114         (clk114),
+//.clk14          (clk14),
+//.clk114         (clk114),
 .clkMuxOut      (clkMuxOut),
 
 // HDMI
@@ -482,10 +489,10 @@ FSX fsx(
 .TMDS_n         (TMDS_n),
 
 // NTSC composite
-.composite      (composite),
+//.composite      (composite),
 
 // Select output method
-.selectOutput   (selectOutput),
+//.selectOutput   (selectOutput),
 
 // VRAM32
 .vram32_addr    (vram32_gpu_addr),
@@ -731,7 +738,7 @@ CPU cpu(
 
 //-----------STATUS LEDS-----------
 assign led_Booted = (PC >= 27'hC02522 | reset);
-assign led_HDMI = (~selectOutput | reset);
+assign led_HDMI = 1'b0; //(~selectOutput | reset);
 assign led_QSPI = (~SPI0_QSPI | reset);
 
 LEDvisualizer #(.MIN_CLK(100000))

Quartus/modules/GPU/FSX.v

@@ -6,8 +6,8 @@ module FSX(
     //Clocks
     input clkPixel,
     input clkTMDShalf,
-    input clk14,
-    input clk114,
+    //input clk14,
+    //input clk114,
     input clkMuxOut,
 
     //HDMI
@@ -15,10 +15,10 @@ module FSX(
     output [3:0] TMDS_n,
 
     //NTSC composite
-    output [7:0] composite,
+    //output [7:0] composite,
 
     //Select output method
-    input selectOutput,
+    //input selectOutput,
 
     //VRAM32
     output [13:0]       vram32_addr,
@@ -44,6 +44,8 @@ module FSX(
     output              frameDrawn
 );
 
+wire selectOutput = 1'b1; // always HDMI, as I no longer wish to include NTSC as a tiny HDMI monitor is now used as primary display
+
 wire [11:0] h_count_hdmi;
 wire [11:0] v_count_hdmi;
 
@@ -71,7 +73,7 @@ TimingGenerator timingGenerator(
     .frameDrawn(frameDrawn_hdmi)
 );
 
-
+/*
 wire [2:0] r_ntsc;
 wire [2:0] g_ntsc;
 wire [1:0] b_ntsc;
@@ -100,7 +102,7 @@ RGB332toNTSC rgb2ntsc(
     .composite(composite), // video output signal
     .frameDrawn(frameDrawn_ntsc) // interrupt signal
 );
-
+*/
 
 wire hsync;
 wire vsync;
@@ -108,12 +110,21 @@ wire blank;
 wire [11:0] h_count;
 wire [11:0] v_count;
 
+/*
 assign frameDrawn   = (selectOutput == 1'b1) ? frameDrawn_hdmi : frameDrawn_ntsc;
 assign hsync        = (selectOutput == 1'b1) ? hsync_hdmi : hsync_ntsc;
 assign vsync        = (selectOutput == 1'b1) ? vsync_hdmi : ~vsync_ntsc; // ntsc vsync is inverted
 assign blank        = (selectOutput == 1'b1) ? blank_hdmi : blank_ntsc;
 assign h_count      = (selectOutput == 1'b1) ? h_count_hdmi : h_count_ntsc;
 assign v_count      = (selectOutput == 1'b1) ? v_count_hdmi : v_count_ntsc;
+*/
+
+assign frameDrawn   = frameDrawn_hdmi;
+assign hsync        = hsync_hdmi;
+assign vsync        = vsync_hdmi;
+assign blank        = blank_hdmi;
+assign h_count      = h_count_hdmi;
+assign v_count      = v_count_hdmi;
 
 
 wire [2:0] BGW_r;
@@ -186,18 +197,25 @@ assign rendered_r = (pxPriority) ? PX_r: BGW_r;
 assign rendered_g = (pxPriority) ? PX_g: BGW_g;
 assign rendered_b = (pxPriority) ? PX_b : BGW_b;
 
+/*
 assign r_ntsc = (!selectOutput) ? rendered_r : 3'd0;
 assign g_ntsc = (!selectOutput) ? rendered_g : 3'd0;
 assign b_ntsc = (!selectOutput) ? rendered_b : 2'd0;
-
+*/
 
 wire [2:0] r_hdmi;
 wire [2:0] g_hdmi;
 wire [1:0] b_hdmi;
 
+/*
 assign r_hdmi = (selectOutput) ? rendered_r : 3'd0;
 assign g_hdmi = (selectOutput) ? rendered_g : 3'd0;
 assign b_hdmi = (selectOutput) ? rendered_b : 2'd0;
+*/
+
+assign r_hdmi = rendered_r;
+assign g_hdmi = rendered_g;
+assign b_hdmi = rendered_b;
 
 wire [7:0] rByte;
 wire [7:0] gByte;
@@ -222,31 +240,70 @@ RGB2HDMI rgb2hdmi(
     .gTMDS  (TMDS_p[1]),
     .rTMDS  (TMDS_p[2]),
     .cTMDS  (TMDS_p[3]),
-	 .bTMDSn  (TMDS_n[0]),
+    .bTMDSn  (TMDS_n[0]),
     .gTMDSn  (TMDS_n[1]),
     .rTMDSn  (TMDS_n[2]),
     .cTMDSn  (TMDS_n[3])
 );
 
-
 /*
 // Image file generator for simulation
 integer file;
 integer framecounter = 0;
+
+// HDMI
 always @(negedge vsync_hdmi)
 begin
-    file = $fopen($sformatf("/home/bart/Documents/FPGA/FPGC5/Verilog/output/frame%0d.ppm", framecounter), "w");
-    $fwrite(file, "P3\n");
-    $fwrite(file, "640 480\n");
-    $fwrite(file, "255\n");
-    framecounter = framecounter + 1;
+    if (selectOutput == 1'b1)
+    begin
+        file = $fopen($sformatf("/home/bart/Documents/FPGA/FPGC6/Verilog/output/frame%0d.ppm", framecounter), "w");
+        $fwrite(file, "P3\n");
+        $fwrite(file, "640 480\n");
+        $fwrite(file, "255\n");
+        framecounter = framecounter + 1;
+    end
+end
+
+always @(posedge clkPixel)
+begin
+    if (selectOutput == 1'b1)
+    begin
+        if (~blank_hdmi)
+        begin
+            $fwrite(file, "%d  %d  %d\n", rByte, gByte, bByte);
+        end
+    end
+end
+*/
+/*
+wire [7:0] rByte_ntsc;
+wire [7:0] gByte_ntsc;
+wire [7:0] bByte_ntsc;
+assign rByte_ntsc = (r_ntsc == 3'd0) ?  {r_ntsc, 5'b00000} : {r_ntsc, 5'b11111};
+assign gByte_ntsc = (g_ntsc == 3'd0) ?  {g_ntsc, 5'b00000} : {g_ntsc, 5'b11111};
+assign bByte_ntsc = (b_ntsc == 2'd0) ?  {b_ntsc, 6'b000000} : {b_ntsc, 6'b111111};
+
+// NTSC
+always @(negedge vsync_ntsc)
+begin
+    if (selectOutput == 1'b0)
+    begin
+        file = $fopen($sformatf("/home/bart/Documents/FPGA/FPGC6/Verilog/output/frame%0d.ppm", framecounter), "w");
+        $fwrite(file, "P3\n");
+        $fwrite(file, "320 240\n");
+        $fwrite(file, "255\n");
+        framecounter = framecounter + 1;
+    end
 end
 
 always @(posedge clkPixel)
 begin
-    if (~blank_hdmi)
+    if (selectOutput == 1'b0)
     begin
-        $fwrite(file, "%d  %d  %d\n", rByte, gByte, bByte);
+        if (~blank_ntsc)
+        begin
+            $fwrite(file, "%d  %d  %d\n", rByte_ntsc, gByte_ntsc, bByte_ntsc);
+        end
     end
 end
 */

Quartus/modules/Memory/L2cache.v

@@ -28,27 +28,29 @@ module L2cache(
 wire cache_reset;
 assign cache_reset = 1'b0;
 
-parameter cache_size = 1024;                // cache size in words. 8129*4bytes = 32KiB
-parameter index_size = 10;                  // index size: log2(cache_size)
-parameter tag_size = 14;                    // mem_add_bits-index_size = 24-13 = 11
+parameter cache_size = 32768;               // cache size in words. 8129*4bytes = 32KiB
+parameter index_size = 15;                  // index size: log2(cache_size)
+parameter tag_size = 9;                     // mem_addr_bits-index_size = 24-13 = 11
 parameter cache_line_size = tag_size+32+1;  // tag + word + valid bit
 
 reg [cache_line_size-1:0] cache [0:cache_size-1];   // cache memory
 
+/*
 integer i;
 // init cache to all zeros
 initial
 begin
     for (i = 0; i < cache_size; i = i + 1)
     begin
-        cache[i] = 47'd0;
+        cache[i] = 42'd0;
     end
 end
+*/
 
-reg [index_size-1:0]        cache_addr = 10'd0;
-reg [cache_line_size-1:0]   cache_d = 47'd0;
+reg [index_size-1:0]        cache_addr = 15'd0;
+reg [cache_line_size-1:0]   cache_d = 42'd0;
 reg                         cache_we = 1'b0;
-reg [cache_line_size-1:0]   cache_q = 47'd0;
+reg [cache_line_size-1:0]   cache_q = 42'd0;
 always @(posedge clk) 
 begin
     cache_q <= cache[cache_addr];
@@ -139,7 +141,7 @@ begin
                 begin
                     clear_cache_counter <= clear_cache_counter + 1'b1;
                     cache_we <= 1'b1;
-                    cache_d <= 47'd0;
+                    cache_d <= 42'd0;
                     cache_addr <= clear_cache_counter;
                 end
                 
@@ -204,7 +206,7 @@ begin
             state_check_cache: 
             begin
                 // check cache. if hit, return cached item
-                if (cache_q[46] && sdc_addr_reg[23:index_size] == cache_q[45:32]) // valid and tag check
+                if (cache_q[41] && sdc_addr_reg[23:index_size] == cache_q[40:32]) // valid and tag check
                 begin
                     state <= state_done_high;
 

Verilog/modules/FPGC6.v

@@ -438,8 +438,8 @@ FSX fsx(
 //Clocks
 .clkPixel       (clkPixel),
 .clkTMDShalf    (clkTMDShalf),
-.clk14          (clk14),
-.clk114         (clk114),
+//.clk14          (clk14),
+//.clk114         (clk114),
 .clkMuxOut      (clkMuxOut),
 
 
@@ -448,10 +448,10 @@ FSX fsx(
 .TMDS_n         (TMDS_n),
 
 //NTSC composite
-.composite      (composite),
+//.composite      (composite),
 
 //Select output method
-.selectOutput   (selectOutput),
+//.selectOutput   (selectOutput),
 
 //VRAM32
 .vram32_addr    (vram32_gpu_addr),

Verilog/modules/GPU/FSX.v

@@ -6,8 +6,8 @@ module FSX(
     //Clocks
     input clkPixel,
     input clkTMDShalf,
-    input clk14,
-    input clk114,
+    //input clk14,
+    //input clk114,
     input clkMuxOut,
 
     //HDMI
@@ -15,10 +15,10 @@ module FSX(
     output [3:0] TMDS_n,
 
     //NTSC composite
-    output [7:0] composite,
+    //output [7:0] composite,
 
     //Select output method
-    input selectOutput,
+    //input selectOutput,
 
     //VRAM32
     output [13:0]       vram32_addr,
@@ -44,6 +44,8 @@ module FSX(
     output              frameDrawn
 );
 
+wire selectOutput = 1'b1; // always HDMI, as I no longer wish to include NTSC as a tiny HDMI monitor is now used as primary display
+
 // LVDS Converter
 wire [3:0] TMDS;
 
@@ -81,7 +83,7 @@ TimingGenerator timingGenerator(
     .frameDrawn(frameDrawn_hdmi)
 );
 
-
+/*
 wire [2:0] r_ntsc;
 wire [2:0] g_ntsc;
 wire [1:0] b_ntsc;
@@ -110,7 +112,7 @@ RGB332toNTSC rgb2ntsc(
     .composite(composite), // video output signal
     .frameDrawn(frameDrawn_ntsc) // interrupt signal
 );
-
+*/
 
 wire hsync;
 wire vsync;
@@ -118,12 +120,22 @@ wire blank;
 wire [11:0] h_count;
 wire [11:0] v_count;
 
+/*
 assign frameDrawn   = (selectOutput == 1'b1) ? frameDrawn_hdmi : frameDrawn_ntsc;
 assign hsync        = (selectOutput == 1'b1) ? hsync_hdmi : hsync_ntsc;
 assign vsync        = (selectOutput == 1'b1) ? vsync_hdmi : ~vsync_ntsc; // ntsc vsync is inverted
 assign blank        = (selectOutput == 1'b1) ? blank_hdmi : blank_ntsc;
 assign h_count      = (selectOutput == 1'b1) ? h_count_hdmi : h_count_ntsc;
 assign v_count      = (selectOutput == 1'b1) ? v_count_hdmi : v_count_ntsc;
+*/
+
+assign frameDrawn   = frameDrawn_hdmi;
+assign hsync        = hsync_hdmi;
+assign vsync        = vsync_hdmi;
+assign blank        = blank_hdmi;
+assign h_count      = h_count_hdmi;
+assign v_count      = v_count_hdmi;
+
 
 
 wire [2:0] BGW_r;
@@ -197,18 +209,25 @@ assign rendered_r = (pxPriority) ? PX_r: BGW_r;
 assign rendered_g = (pxPriority) ? PX_g: BGW_g;
 assign rendered_b = (pxPriority) ? PX_b : BGW_b;
 
+/*
 assign r_ntsc = (!selectOutput) ? rendered_r : 3'd0;
 assign g_ntsc = (!selectOutput) ? rendered_g : 3'd0;
 assign b_ntsc = (!selectOutput) ? rendered_b : 2'd0;
-
+*/
 
 wire [2:0] r_hdmi;
 wire [2:0] g_hdmi;
 wire [1:0] b_hdmi;
 
+/*
 assign r_hdmi = (selectOutput) ? rendered_r : 3'd0;
 assign g_hdmi = (selectOutput) ? rendered_g : 3'd0;
 assign b_hdmi = (selectOutput) ? rendered_b : 2'd0;
+*/
+
+assign r_hdmi = rendered_r;
+assign g_hdmi = rendered_g;
+assign b_hdmi = rendered_b;
 
 wire [7:0] rByte;
 wire [7:0] gByte;
@@ -264,6 +283,7 @@ begin
     end
 end
 
+/*
 wire [7:0] rByte_ntsc;
 wire [7:0] gByte_ntsc;
 wire [7:0] bByte_ntsc;
@@ -294,5 +314,6 @@ begin
         end
     end
 end
+*/
 
 endmodule

Verilog/modules/Memory/L2cache.v

@@ -28,9 +28,9 @@ module L2cache(
 wire cache_reset;
 assign cache_reset = 1'b0;
 
-parameter cache_size = 1024;                // cache size in words. 8129*4bytes = 32KiB
-parameter index_size = 10;                  // index size: log2(cache_size)
-parameter tag_size = 14;                    // mem_add_bits-index_size = 24-13 = 11
+parameter cache_size = 32768;               // cache size in words. 8129*4bytes = 32KiB
+parameter index_size = 15;                  // index size: log2(cache_size)
+parameter tag_size = 9;                     // mem_addr_bits-index_size = 24-13 = 11
 parameter cache_line_size = tag_size+32+1;  // tag + word + valid bit
 
 reg [cache_line_size-1:0] cache [0:cache_size-1];   // cache memory
@@ -41,14 +41,14 @@ initial
 begin
     for (i = 0; i < cache_size; i = i + 1)
     begin
-        cache[i] = 47'd0;
+        cache[i] = 42'd0;
     end
 end
 
-reg [index_size-1:0]        cache_addr = 10'd0;
-reg [cache_line_size-1:0]   cache_d = 47'd0;
+reg [index_size-1:0]        cache_addr = 15'd0;
+reg [cache_line_size-1:0]   cache_d = 42'd0;
 reg                         cache_we = 1'b0;
-reg [cache_line_size-1:0]   cache_q = 47'd0;
+reg [cache_line_size-1:0]   cache_q = 42'd0;
 always @(posedge clk) 
 begin
     cache_q <= cache[cache_addr];
@@ -139,7 +139,7 @@ begin
                 begin
                     clear_cache_counter <= clear_cache_counter + 1'b1;
                     cache_we <= 1'b1;
-                    cache_d <= 47'd0;
+                    cache_d <= 42'd0;
                     cache_addr <= clear_cache_counter;
                 end
                 
@@ -204,7 +204,7 @@ begin
             state_check_cache: 
             begin
                 // check cache. if hit, return cached item
-                if (cache_q[46] && sdc_addr_reg[23:index_size] == cache_q[45:32]) // valid and tag check
+                if (cache_q[41] && sdc_addr_reg[23:index_size] == cache_q[40:32]) // valid and tag check
                 begin
                     state <= state_done_high;
 

Verilog/output/FPGC.gtkw

@@ -1,22 +1,22 @@
 [*]
 [*] GTKWave Analyzer v3.3.107 (w)1999-2020 BSI
-[*] Sat Sep  2 15:51:57 2023
+[*] Sat Sep  2 21:10:16 2023
 [*]
 [dumpfile] "/home/bart/Documents/FPGA/FPGC6/Verilog/output/wave.vcd"
-[dumpfile_mtime] "Sat Sep  2 15:42:56 2023"
-[dumpfile_size] 48021003
+[dumpfile_mtime] "Sat Sep  2 16:09:11 2023"
+[dumpfile_size] 46133170
 [savefile] "/home/bart/Documents/FPGA/FPGC6/Verilog/output/FPGC.gtkw"
-[timestart] 0
+[timestart] 25540000
 [size] 1920 1054
 [pos] -1 -1
-*-26.666576 407400000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-21.666576 1263700 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] FPGC_tb.
 [treeopen] FPGC_tb.fpgc.
 [treeopen] FPGC_tb.fpgc.cpu.arbiter.
 [sst_width] 227
 [signals_width] 366
 [sst_expanded] 1
-[sst_vpaned_height] 495
+[sst_vpaned_height] 494
 @28
 FPGC_tb.fpgc.clk
 @22
@@ -56,6 +56,7 @@ FPGC_tb.fpgc.cpu.arbiter.bus_data[31:0]
 @28
 FPGC_tb.fpgc.cpu.arbiter.bus_we
 FPGC_tb.fpgc.cpu.arbiter.bus_start
+@29
 FPGC_tb.fpgc.cpu.arbiter.bus_done
 @200
 -
@@ -296,7 +297,7 @@ FPGC_tb.fpgc.l2cache.state[2:0]
 FPGC_tb.fpgc.l2cache.clear_cache_counter[15:0]
 @200
 -
-@29
+@28
 FPGC_tb.fpgc.l2cache.start_registered
 @24
 FPGC_tb.fpgc.l2cache.cache_addr[9:0]