Documentation update. Remove subl3 files.

Signed-off-by: bartpleiter <a.t.pleiter@gmail.com>

Documentation/docs/Build-instructions/verilog.md

@@ -1,6 +1,6 @@
 # Verilog build/simulate instructions
 
-To simulate the design, iverilog is used. You might need to compile the latest version yourself.
+To simulate the design, iverilog is used. Use version >= 12.0
 
 To run the simulation (in this case a testbench of the entire FPGC), run 
 
@@ -10,6 +10,18 @@ iverilog -o /home/bart/Documents/FPGA/FPGC6/Verilog/output/output \
   && vvp /home/bart/Documents/FPGA/FPGC6/Verilog/output/output
 ```
 
-Assuming the testbench generates a `wave.vcd`, run `GTKWave` with this file as argument (or open the file within the program).
+Display statements will be printed to the terminal by `vvp`.
+
+![vvp](../images/vvp.png)
+
+## Waveform viewer
+
+Assuming the testbench generates a `wave.vcd`, you can use `GTKWave` to view the waveform.
+
+```bash
+gtkwave /home/bart/Documents/FPGA/FPGC6/Verilog/output/FPGC.gtkw --dark
+```
+
+![GTKwave](../images/gtkwave.png)
 
 Tip: use `ctrl+shft+b` to reload the waveform when overwritten by a new simulation.

SublimeText3/b32p.sublime-build

@@ -1,8 +0,0 @@
-{ 
-	
-	"cmd" : ["bash buildToVerilog.sh"],
-	//"cmd" : ["bash simulate.sh"],
-	"shell": true,
-	"working_dir": "${file_path}",
-	"file_patterns": ["*.asm"]
-}

SublimeText3/python3.sublime-build

@@ -1,6 +0,0 @@
-{
- "cmd": ["/usr/bin/python3", "-u", "$file"],
- "file_regex": "^[ ]File \"(...?)\", line ([0-9]*)",
- "selector": "source.python",
- "file_patterns": ["*.py"]
-}

SublimeText3/verilog.sublime-build

@@ -1,8 +0,0 @@
-//my static compile script, will not work on practically any other PC, so modify the path to your files
-//it is static so I can compile my testbench while not having to switch tabs to the testbench file
-{
-//	"shell_cmd": "iverilog -o /home/bart/Documents/FPGA/FPGC6/Verilog/output/output /home/bart/Documents/FPGA/FPGC6/Verilog/testbench/B32P_tb.v && vvp /home/bart/Documents/FPGA/FPGC6/Verilog/output/output",
-	"shell_cmd": "iverilog -o /home/bart/Documents/FPGA/FPGC6/Verilog/output/output /home/bart/Documents/FPGA/FPGC6/Verilog/testbench/FPGC_tb.v && vvp /home/bart/Documents/FPGA/FPGC6/Verilog/output/output",
-	"file_patterns": ["*.v"]
-}
-//also, you can use $file for current file

Verilog/testbench/FPGC_tb.v

@@ -10,8 +10,8 @@
 `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/FPGC6.v"
 
 // other logic
-`include "/home/bart/Documents/FPGA/FPGC5/Verilog/modules/MultiStabilizer.v"
-`include "/home/bart/Documents/FPGA/FPGC5/Verilog/modules/DtrReset.v"
+`include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/MultiStabilizer.v"
+`include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/DtrReset.v"
 
 // cpu
 `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/CPU.v"