Initial setup to simulate 100mhz cpu in verilog testbench.

Assembler/simulate.sh

@@ -1,9 +1,9 @@
-# Build script for assembly files for simulation in verilog (run from ROM)
-if (python3 Assembler.py bdos 0xC02522 > ../Verilog/memory/rom.list) # compile and write to verilog memory folder
+# Build script for assembly files for simulation in verilog (run from SRAM)
+if (python3 Assembler.py bdos 0x000000 > ../Verilog/memory/sram.list) # compile and write to verilog memory folder
     then
-        iverilog -o /home/bart/Documents/FPGA/FPGC6/Verilog/output/output /home/bart/Documents/FPGA/FPGC6/Verilog/testbench/FPGC_tb.v
+        iverilog -o /home/bart/Documents/FPGA/FPGC6/Verilog/output/output /home/bart/Documents/FPGA/FPGC6/Verilog/testbench/FPGC_100MHz_tb.v
         vvp /home/bart/Documents/FPGA/FPGC6/Verilog/output/output
     else
         # print the error, which is in code.list
-        (cat ../Verilog/memory/rom.list)
+        (cat ../Verilog/memory/sram.list)
 fi

Documentation/docs/Build-instructions/verilog.md

@@ -24,4 +24,4 @@ gtkwave /home/bart/Documents/FPGA/FPGC6/Verilog/output/FPGC.gtkw --dark
 
 ![GTKwave](../images/gtkwave.png)
 
-Tip: use `ctrl+shft+b` to reload the waveform when overwritten by a new simulation.
+Tip: use `ctrl+shft+r` to reload the waveform when overwritten by a new simulation.

Documentation/docs/Hardware/Logic/CPU (B32P)/pipeline.md

@@ -7,6 +7,9 @@ The B32P has a 5-stage pipeline, very similar to a MIPS CPU. The stages are as f
 - MEM (memory access): Stack access and memory bus access
 - WB (write back): Write to register bank
 
+A full schematic overview of how all the CPU components fall within this pipeline can be seen in this image. (You might want to right-click the image and open in a new tab to zoom in)
+![CPU architecture](../../../images/CPU_arch.jpg)
+
 ## Hazard detection and branch prediction
 The CPU detects pipeline hazards, removing the need for the programmer to account for this, by doing the following things depending on the situation:
 

Verilog/memory/sram.list

@@ -0,0 +1,9 @@
+10010000000000000000000000001000 //Jump to constant address 4
+10010000000000000000000000010000 //Jump to constant address 8
+10010000000000000000000000001000 //Jump to constant address 4
+10010000000000000000000000001000 //Jump to constant address 4
+00011100000000000000010100010001 //Set r1 to 5
+00011100000000000000011100100010 //Set r2 to 7
+00000011000000000000000100100011 //Compute r1 + r2 and write result to r3
+11111111111111111111111111111111 //Halt
+01000000000000000000000000000000 //Return from interrupt

Verilog/modules/CPU/CPU.v

@@ -32,20 +32,13 @@ module CPU(
     input [31:0]  bus_q,
     input         bus_done,
 
-    // sdram bus
-    output [23:0] sdc_addr,     // bus_addr
-    output [31:0] sdc_data,     // bus_data
-    output        sdc_we,       // bus_we
-    output        sdc_start,    // bus_start
-    input [31:0]  sdc_q,        // bus_q
-    input         sdc_done,     // bus_done
-
     input int1, int2, int3, int4, int5, int6, int7, int8, int9, int10,
 
-    output [26:0] PC
+    output reg    led
 );
 
-parameter PCstart = 27'hC02522; // internal ROM addr 0 //27'hC02522;
+parameter PCstart = 27'h000000; // internal SRAM addr 0 //27'h000000;
+parameter PCinterruptValidFrom = 27'd100; // interrupt valid after address 100
 parameter PCincrease = 1'b1; // number of addresses to increase the PC with after each instruction
 parameter InterruptJumpAddr = 27'd1;
 
@@ -75,18 +68,14 @@ wire [31:0] arbiter_bus_q;        // bus_q
 wire        arbiter_bus_done;     // bus_done
 
 // bus splitter
-assign sdc_addr =   (arbiter_bus_addr < 27'h800000) ? arbiter_bus_addr: 24'd0;
-assign sdc_data =   (arbiter_bus_addr < 27'h800000) ? arbiter_bus_data: 32'd0;
-assign sdc_we =     (arbiter_bus_addr < 27'h800000) ? arbiter_bus_we: 1'b0;
-assign sdc_start =  (arbiter_bus_addr < 27'h800000) ? arbiter_bus_start: 1'b0;
 
-assign bus_addr =   (arbiter_bus_addr < 27'h800000) ? 27'd0: arbiter_bus_addr;
-assign bus_data =   (arbiter_bus_addr < 27'h800000) ? 32'd0: arbiter_bus_data;
-assign bus_we =     (arbiter_bus_addr < 27'h800000) ? 1'b0: arbiter_bus_we;
-assign bus_start =  (arbiter_bus_addr < 27'h800000) ? 1'b0: arbiter_bus_start;
+assign bus_addr =   arbiter_bus_addr;
+assign bus_data =   arbiter_bus_data;
+assign bus_we =     arbiter_bus_we;
+assign bus_start =  arbiter_bus_start;
 
-assign arbiter_bus_q =      (arbiter_bus_addr < 27'h800000) ? sdc_q: bus_q;
-assign arbiter_bus_done =   (arbiter_bus_addr < 27'h800000) ? sdc_done: bus_done;
+assign arbiter_bus_q =      bus_q;
+assign arbiter_bus_done =   bus_done;
 
 Arbiter arbiter (
 .clk(clk),
@@ -169,7 +158,6 @@ reg [31:0]  pc_FE_backup = 32'd0;
 wire [31:0] pc4_FE;
 assign pc4_FE = pc_FE + 1'b1;
 
-assign PC = pc_FE;
 
 wire [31:0] PC_backup_current;
 assign PC_backup_current = pc4_EX - PCincrease;
@@ -179,7 +167,7 @@ assign PC_backup_current = pc4_EX - PCincrease;
 assign interruptValid = (
     intCPU && 
     !intDisabled && 
-    PC_backup_current < PCstart && 
+    PC_backup_current >= PCinterruptValidFrom && 
     (
         branch_MEM || jumpr_MEM || jumpc_MEM || halt_MEM
     )
@@ -224,38 +212,6 @@ begin
 end
 
 
-//------------L1i Cache--------------
-//CPU bus
-wire [31:0]      l1i_addr;  // address to write or to start reading from
-wire [31:0]      l1i_data;  // data to write
-wire             l1i_we;    // write enable
-wire             l1i_start; // start trigger
-wire [31:0]      l1i_q;     // memory output
-wire             l1i_done;  // output ready
-
-L1Icache l1icache(
-.clk            (clk),
-.reset          (reset),
-.cache_reset    (clearCache_EX | clearCache_MEM),
-
-// CPU bus
-.l2_addr       (l1i_addr),
-.l2_data       (l1i_data),
-.l2_we         (l1i_we),
-.l2_start      (l1i_start),
-.l2_q          (l1i_q),
-.l2_done       (l1i_done),
-
-// sdram bus
-.sdc_addr       (addr_a),
-.sdc_data       (data_a),
-.sdc_we         (we_a),
-.sdc_start      (start_a),
-.sdc_q          (arbiter_q),
-.sdc_done       (done_a)
-);
-
-
 // Instruction Memory
 //  should eventually become a memory with variable latency
 // writes directly to next stage
@@ -269,12 +225,12 @@ InstrMem instrMem(
 .hit(instr_hit_FE),
 
 // bus
-.bus_addr(l1i_addr),
-.bus_data(l1i_data),
-.bus_we(l1i_we),
-.bus_start(l1i_start),
-.bus_q(l1i_q),
-.bus_done(l1i_done),
+.bus_addr(addr_a),
+.bus_data(data_a),
+.bus_we(we_a),
+.bus_start(start_a),
+.bus_q(arbiter_q),
+.bus_done(done_a),
 
 .hold(stall_FE),
 .clear(flush_FE)
@@ -659,36 +615,7 @@ begin
     endcase
 end
 
-//------------L1d Cache--------------
-//CPU bus
-wire [31:0]      l1d_addr;  // address to write or to start reading from
-wire [31:0]      l1d_data;  // data to write
-wire             l1d_we;    // write enable
-wire             l1d_start; // start trigger
-wire [31:0]      l1d_q;     // memory output
-wire             l1d_done;  // output ready
-
-L1Dcache l1dcache(
-.clk            (clk),
-.reset          (reset),
-.cache_reset    (clearCache_EX | clearCache_MEM),
-
-// CPU bus
-.l2_addr       (l1d_addr),
-.l2_data       (l1d_data),
-.l2_we         (l1d_we),
-.l2_start      (l1d_start),
-.l2_q          (l1d_q),
-.l2_done       (l1d_done),
-
-// sdram bus
-.sdc_addr       (addr_b),
-.sdc_data       (data_b),
-.sdc_we         (we_b),
-.sdc_start      (start_b),
-.sdc_q          (arbiter_q),
-.sdc_done       (done_b)
-);
+
 
 
 // Data Memory
@@ -709,12 +636,12 @@ DataMem dataMem(
 .busy(datamem_busy_MEM),
 
 // bus
-.bus_addr(l1d_addr),
-.bus_data(l1d_data),
-.bus_we(l1d_we),
-.bus_start(l1d_start),
-.bus_q(l1d_q),
-.bus_done(l1d_done),
+.bus_addr(addr_b),
+.bus_data(data_b),
+.bus_we(we_b),
+.bus_start(start_b),
+.bus_q(arbiter_q),
+.bus_done(done_b),
 
 .hold(stall_MEM),
 .clear(flush_MEM)
@@ -906,4 +833,9 @@ begin
 end
 
 
+always @(posedge clk)
+begin
+    led <= pc_FE[0];
+end
+
 endmodule

Verilog/modules/FPGC6.v

@@ -2,489 +2,27 @@
 * Top level design of the FPGC6
 */
 module FPGC6(
-    input           clk, //50MHz
-    input           clk_SDRAM, //100MHz
+    input           clk, // 100MHz
     input           nreset,
-
-    //HDMI
-    output wire [3:0] TMDS_p,
-    output wire [3:0] TMDS_n,
-
-    //SDRAM
-    output          SDRAM_CLK,
-    output          SDRAM_CSn,
-    output          SDRAM_WEn,
-    output          SDRAM_CASn,
-    output          SDRAM_RASn,
-    output          SDRAM_CKE,
-    output [12:0]   SDRAM_A,
-    output [1:0]    SDRAM_BA,
-    output [3:0]    SDRAM_DQM,
-    inout  [31:0]   SDRAM_DQ,
-
-    //SPI0 flash
-    output          SPI0_clk,
-    output          SPI0_cs,
-    inout           SPI0_data,
-    inout           SPI0_q,
-    inout           SPI0_wp,
-    inout           SPI0_hold,
-     
-    //SPI1 CH376 bottom
-    output          SPI1_clk,
-    output          SPI1_cs,
-    output          SPI1_mosi,
-    input           SPI1_miso,
-    input           SPI1_nint,
-    output          SPI1_rst,
-     
-    //SPI2 CH376 top
-    output          SPI2_clk,
-    output          SPI2_cs,
-    output          SPI2_mosi,
-    input           SPI2_miso,
-    input           SPI2_nint,
-    output          SPI2_rst,
-     
-    //SPI3 W5500
-    output          SPI3_clk,
-    output          SPI3_cs,
-    output          SPI3_mosi,
-    input           SPI3_miso,
-    input           SPI3_int,
-    output          SPI3_nrst,
-     
-    //SPI4 GP
-    output          SPI4_clk,
-    output          SPI4_cs,
-    output          SPI4_mosi,
-    input           SPI4_miso,
-    input           SPI4_gp,
-     
-    //UART0
-    input           UART0_in,
-    output          UART0_out,
-    input           UART0_dtr,
-     
-    //UART1 (currently unused because no UART midi synth anymore)
-    //input           UART1_in,
-    //output          UART1_out,
-     
-    //UART2
-    input           UART2_in,
-    output          UART2_out,
-     
-    //PS/2
-    input           PS2_clk, PS2_data,
-     
-    //Led for debugging
-    output          led,
-     
-    //GPIO
-    input [3:0]     GPI,
-    output [3:0]    GPO,
-     
-    //DIP switch
-    input [3:0]     DIPS,
-
-    //I2S audio
-    output          I2S_SDIN, I2S_SCLK, I2S_LRCLK, I2S_MCLK,
     
-    //Status leds
-    output          led_Booted, led_Eth, led_Flash, led_USB0, led_USB1, led_PS2, led_HDMI, led_QSPI, led_GPU, led_I2S
+    //Led for debugging
+    output          led
 );
 
-
-// TMP FIXES FOR NEW PCB
-assign I2S_SDIN = 1'b0;
-assign I2S_SCLK = 1'b0;
-assign I2S_LRCLK = 1'b0;
-assign I2S_MCLK = 1'b0;
-
-
-//-------------------CLK-------------------------
-//In hardware a PLL should be used here
-// to create the clk and crt_clk 
-//assign crt_clk = clk; //'fix' for simulation
-
-//Run VGA at CRT speed
-//assign vga_clk = crt_clk;
-
-wire clkTMDShalf;   // TMDS clock (pre-DDR), 5x pixel clock
-wire clkPixel;  // Pixel clock
-
-wire clk14; // NTSC clock
-wire clk114; // NTSC color clock
-
-wire clkMuxOut; // HDMI or NTSC clock, depending on selectOutput
-
-// everything at clk speed for simulation
-assign clkTMDShalf = clk;
-assign clkPixel = clk;
-assign clk14 = clk;
-assign clk114 = clk;
-assign clkMuxOut = clk;
-
-//Run SDRAM at 100MHz
-assign SDRAM_CLK = clk_SDRAM;
-
-
 //--------------------Reset&Stabilizers-----------------------
 //Reset signals
-wire nreset_stable, UART0_dtr_stable, reset;
-
-//Dip switch
-wire boot_mode_stable;
-
-//GPU: High when frame just rendered (needs to be stabilized)
-wire frameDrawn, frameDrawn_stable;
-
-//Stabilized SPI interrupt signals
-wire SPI1_nint_stable, SPI2_nint_stable, SPI3_int_stable, SPI4_gp_stable; 
+wire nreset_stable, reset;
 
 MultiStabilizer multistabilizer (
 .clk(clk),
 .u0(nreset),
-.s0(nreset_stable),
-.u1(UART0_dtr),
-.s1(UART0_dtr_stable),
-.u2(SPI1_nint),
-.s2(SPI1_nint_stable),
-.u3(SPI2_nint),
-.s3(SPI2_nint_stable),
-.u4(SPI3_int),
-.s4(SPI3_int_stable),
-.u5(SPI4_gp),
-.s5(SPI4_gp_stable),
-.u6(frameDrawn),
-.s6(frameDrawn_stable),
-.u7(DIPS[0]),
-.s7(boot_mode_stable)
-);
-
-//Indicator for opened Serial port
-assign led = UART0_dtr_stable;
-
-//DRT to reset pulse
-wire dtrRst;
-
-DtrReset dtrReset (
-.clk(clk),
-.dtr(UART0_dtr_stable),
-.dtrRst(dtrRst)
-);
-
-assign reset = (~nreset_stable) || dtrRst;
-
-//External reset outputs
-assign SPI1_rst = reset;
-assign SPI2_rst = reset;
-assign SPI3_nrst = ~reset;
-
-
-//---------------------------VRAM32---------------------------------
-//VRAM32 I/O
-wire        vram32_gpu_clk;
-wire [13:0] vram32_gpu_addr;
-wire [31:0] vram32_gpu_d;
-wire        vram32_gpu_we;
-wire [31:0] vram32_gpu_q;
-
-wire        vram32_cpu_clk;
-wire [13:0] vram32_cpu_addr;
-wire [31:0] vram32_cpu_d;
-wire        vram32_cpu_we; 
-wire [31:0] vram32_cpu_q;
-
-//because FSX will not write to VRAM
-assign vram32_gpu_we    = 1'b0;
-assign vram32_gpu_d     = 32'd0;
-
-VRAM #(
-.WIDTH(32),
-.WORDS(1056),
-.ADDR_BITS(14),
-.LIST("/home/bart/Documents/FPGA/FPGC6/Verilog/memory/vram32.list")
-)   vram32(
-//CPU port
-.cpu_clk    (clk),
-.cpu_d      (vram32_cpu_d),
-.cpu_addr   (vram32_cpu_addr),
-.cpu_we     (vram32_cpu_we),
-.cpu_q      (vram32_cpu_q),
-
-//GPU port
-.gpu_clk    (clkMuxOut),
-.gpu_d      (vram32_gpu_d),
-.gpu_addr   (vram32_gpu_addr),
-.gpu_we     (vram32_gpu_we),
-.gpu_q      (vram32_gpu_q)
-);
-
-
-//---------------------------VRAM322--------------------------------
-//VRAM322 I/O
-wire        vram322_gpu_clk;
-wire [13:0] vram322_gpu_addr;
-wire [31:0] vram322_gpu_d;
-wire        vram322_gpu_we;
-wire [31:0] vram322_gpu_q;
-
-//because FSX will not write to VRAM
-assign vram322_gpu_we    = 1'b0;
-assign vram322_gpu_d     = 32'd0;
-
-VRAM #(
-.WIDTH(32),
-.WORDS(1056),
-.ADDR_BITS(14),
-.LIST("/home/bart/Documents/FPGA/FPGC6/Verilog/memory/vram32.list")
-)   vram322(
-//CPU port
-.cpu_clk    (clk),
-.cpu_d      (vram32_cpu_d),
-.cpu_addr   (vram32_cpu_addr),
-.cpu_we     (vram32_cpu_we),
-.cpu_q      (),
-
-//GPU port
-.gpu_clk    (clkMuxOut),
-.gpu_d      (vram322_gpu_d),
-.gpu_addr   (vram322_gpu_addr),
-.gpu_we     (vram322_gpu_we),
-.gpu_q      (vram322_gpu_q)
-);
-
-
-//--------------------------VRAM8--------------------------------
-//VRAM8 I/O
-wire        vram8_gpu_clk;
-wire [13:0] vram8_gpu_addr;
-wire [7:0]  vram8_gpu_d;
-wire        vram8_gpu_we;
-wire [7:0]  vram8_gpu_q;
-
-wire        vram8_cpu_clk;
-wire [13:0] vram8_cpu_addr;
-wire [7:0]  vram8_cpu_d;
-wire        vram8_cpu_we;
-wire [7:0]  vram8_cpu_q;
-
-//because FSX will not write to VRAM
-assign vram8_gpu_we     = 1'b0;
-assign vram8_gpu_d      = 8'd0;
-
-VRAM #(
-.WIDTH(8),
-.WORDS(8194),
-.ADDR_BITS(14),
-.LIST("/home/bart/Documents/FPGA/FPGC6/Verilog/memory/vram8.list")
-)   vram8(
-//CPU port
-.cpu_clk    (clk),
-.cpu_d      (vram8_cpu_d),
-.cpu_addr   (vram8_cpu_addr),
-.cpu_we     (vram8_cpu_we),
-.cpu_q      (vram8_cpu_q),
-
-//GPU port
-.gpu_clk    (clkMuxOut),
-.gpu_d      (vram8_gpu_d),
-.gpu_addr   (vram8_gpu_addr),
-.gpu_we     (vram8_gpu_we),
-.gpu_q      (vram8_gpu_q)
-);
-
-
-//--------------------------VRAMSPR--------------------------------
-//VRAMSPR I/O
-wire        vramSPR_gpu_clk;
-wire [13:0] vramSPR_gpu_addr;
-wire [8:0]  vramSPR_gpu_d;
-wire        vramSPR_gpu_we;
-wire [8:0]  vramSPR_gpu_q;
-
-wire        vramSPR_cpu_clk;
-wire [13:0] vramSPR_cpu_addr;
-wire [8:0]  vramSPR_cpu_d;
-wire        vramSPR_cpu_we;
-wire [8:0]  vramSPR_cpu_q;
-
-//because FSX will not write to VRAM
-assign vramSPR_gpu_we     = 1'b0;
-assign vramSPR_gpu_d      = 9'd0;
-
-VRAM #(
-.WIDTH(9),
-.WORDS(256),
-.ADDR_BITS(14),
-.LIST("/home/bart/Documents/FPGA/FPGC6/Verilog/memory/vramSPR.list")
-)   vramSPR(
-//CPU port
-.cpu_clk    (clk),
-.cpu_d      (vramSPR_cpu_d),
-.cpu_addr   (vramSPR_cpu_addr),
-.cpu_we     (vramSPR_cpu_we),
-.cpu_q      (vramSPR_cpu_q),
-
-//GPU port
-.gpu_clk    (clkMuxOut),
-.gpu_d      (vramSPR_gpu_d),
-.gpu_addr   (vramSPR_gpu_addr),
-.gpu_we     (vramSPR_gpu_we),
-.gpu_q      (vramSPR_gpu_q)
-);
-
-
-//--------------------------VRAMPX--------------------------------
-//VRAMPX I/O
-wire        vramPX_gpu_clk;
-wire [16:0] vramPX_gpu_addr;
-wire [23:0]  vramPX_gpu_d;
-wire        vramPX_gpu_we;
-wire [23:0]  vramPX_gpu_q;
-
-wire        vramPX_cpu_clk;
-wire [16:0] vramPX_cpu_addr;
-wire [23:0]  vramPX_cpu_d;
-wire        vramPX_cpu_we;
-wire [23:0]  vramPX_cpu_q;
-
-// FSX will not write to VRAM
-assign vramPX_gpu_we     = 1'b0;
-assign vramPX_gpu_d      = 24'd0;
-
-VRAM #(
-.WIDTH(24),
-.WORDS(76800),
-.ADDR_BITS(17),
-.LIST("memory/vramPX.list")
-) vramPX(
-// CPU port
-.cpu_clk    (clk),
-.cpu_d      (vramPX_cpu_d),
-.cpu_addr   (vramPX_cpu_addr),
-.cpu_we     (vramPX_cpu_we),
-.cpu_q      (vramPX_cpu_q),
-
-// GPU port
-.gpu_clk    (clkMuxOut),
-.gpu_d      (vramPX_gpu_d),
-.gpu_addr   (vramPX_gpu_addr),
-.gpu_we     (vramPX_gpu_we),
-.gpu_q      (vramPX_gpu_q)
-);
-
-
-//-------------------ROM-------------------------
-//ROM I/O
-wire [8:0] rom_addr;
-wire [31:0] rom_q;
-
-
-ROM rom(
-.clk            (clk),
-.reset          (reset),
-.address        (rom_addr),
-.q              (rom_q)
-);
-
-
-//----------------SDRAM Controller------------------
-// inputs
-wire [23:0]      sdc_addr;  // address to write or to start reading from
-wire [31:0]      sdc_data;  // data to write
-wire             sdc_we;    // write enable
-wire             sdc_start; // start trigger
-
-// outputs
-wire [31:0]     sdc_q;      // memory output
-wire            sdc_done;   // output ready
-
-SDRAMcontroller sdramcontroller(
-// clock/reset inputs
-.clk        (clk_SDRAM),
-.reset      (reset),
-
-// interface inputs
-.sdc_addr   (sdc_addr),
-.sdc_data   (sdc_data),
-.sdc_we     (sdc_we),
-.sdc_start  (sdc_start),
-
-// interface outputs
-.sdc_q      (sdc_q),
-.sdc_done   (sdc_done),
-
-// SDRAM signals
-.SDRAM_CKE  (SDRAM_CKE),
-.SDRAM_CSn  (SDRAM_CSn),
-.SDRAM_WEn  (SDRAM_WEn),
-.SDRAM_CASn (SDRAM_CASn),
-.SDRAM_RASn (SDRAM_RASn),
-.SDRAM_A    (SDRAM_A),
-.SDRAM_BA   (SDRAM_BA),
-.SDRAM_DQM  (SDRAM_DQM),
-.SDRAM_DQ   (SDRAM_DQ)
+.s0(nreset_stable)
 );
 
+assign reset = ~nreset_stable;
 
-//-----------------------FSX-------------------------
-//FSX I/O
-wire [7:0]  composite; // NTSC composite video signal
-reg         selectOutput = 1'b1; // 1 -> HDMI, 0 -> Composite
-wire        halfRes;
 
-FSX fsx(
-//Clocks
-.clkPixel       (clkPixel),
-.clkTMDShalf    (clkTMDShalf),
-//.clk14          (clk14),
-//.clk114         (clk114),
-.clkMuxOut      (clkMuxOut),
-
-
-//HDMI
-.TMDS_p         (TMDS_p),
-.TMDS_n         (TMDS_n),
-
-//NTSC composite
-//.composite      (composite),
-
-//Select output method
-//.selectOutput   (selectOutput),
-
-.halfRes(halfRes),
-
-//VRAM32
-.vram32_addr    (vram32_gpu_addr),
-.vram32_q       (vram32_gpu_q),
-
-//VRAM32
-.vram322_addr   (vram322_gpu_addr),
-.vram322_q      (vram322_gpu_q),
-
-//VRAM8
-.vram8_addr     (vram8_gpu_addr),
-.vram8_q        (vram8_gpu_q),
-
-//VRAMSPR
-.vramSPR_addr   (vramSPR_gpu_addr),
-.vramSPR_q      (vramSPR_gpu_q),
-
-//VRAMPX
-.vramPX_addr   (vramPX_gpu_addr),
-.vramPX_q      (vramPX_gpu_q),
-
-//Interrupt signal
-.frameDrawn     (frameDrawn)
-);
-
-
-//----------------Memory Unit--------------------
-//Memory Unit I/O
-
-//Bus
+// Bus
 wire [26:0] bus_addr;
 wire [31:0] bus_data;
 wire        bus_we;
@@ -492,180 +30,21 @@ wire        bus_start;
 wire [31:0] bus_q;
 wire        bus_done;
 
-//Interrupt signals
-wire        OST1_int, OST2_int, OST3_int;
-wire        UART0_rx_int, UART2_rx_int;
-wire        PS2_int;
-wire        SPI0_QSPI;
-
-MemoryUnit mu(
-//clock
+MemoryUnit memoryunit(
+// Clocks
 .clk            (clk),
 .reset          (reset),
 
-//CPU connection (Bus)
+// Bus
 .bus_addr       (bus_addr),
 .bus_data       (bus_data),
 .bus_we         (bus_we),
 .bus_start      (bus_start),
 .bus_q          (bus_q),
-.bus_done       (bus_done),
-
-/********
-* MEMORY
-********/
-
-//SPI Flash / SPI0
-.SPIflash_data  (SPI0_data), 
-.SPIflash_q     (SPI0_q), 
-.SPIflash_wp    (SPI0_wp), 
-.SPIflash_hold  (SPI0_hold),
-.SPIflash_cs    (SPI0_cs), 
-.SPIflash_clk   (SPI0_clk),
-
-//VRAM32 cpu port
-.VRAM32_cpu_d       (vram32_cpu_d),
-.VRAM32_cpu_addr    (vram32_cpu_addr), 
-.VRAM32_cpu_we      (vram32_cpu_we),
-.VRAM32_cpu_q       (vram32_cpu_q),
-
-//VRAM8 cpu port
-.VRAM8_cpu_d        (vram8_cpu_d),
-.VRAM8_cpu_addr     (vram8_cpu_addr), 
-.VRAM8_cpu_we       (vram8_cpu_we),
-.VRAM8_cpu_q        (vram8_cpu_q),
-
-//VRAMspr cpu port
-.VRAMspr_cpu_d      (vramSPR_cpu_d),
-.VRAMspr_cpu_addr   (vramSPR_cpu_addr), 
-.VRAMspr_cpu_we     (vramSPR_cpu_we),
-.VRAMspr_cpu_q      (vramSPR_cpu_q),
-
-// VRAMpx cpu port
-.VRAMpx_cpu_d      (vramPX_cpu_d),
-.VRAMpx_cpu_addr   (vramPX_cpu_addr),
-.VRAMpx_cpu_we     (vramPX_cpu_we),
-.VRAMpx_cpu_q      (vramPX_cpu_q),
-
-//ROM
-.ROM_addr           (rom_addr),
-.ROM_q              (rom_q),
-
-/********
-* I/O
-********/
-
-//UART0 (Main USB)
-.UART0_in           (UART0_in),
-.UART0_out          (UART0_out),
-.UART0_rx_interrupt (UART0_rx_int),
-
-//UART1 (APU)
-/*.UART1_in           (),
-.UART1_out          (),
-.UART1_rx_interrupt (),
-*/
-
-//UART2 (GP)
-.UART2_in           (UART2_in),
-.UART2_out          (UART2_out),
-.UART2_rx_interrupt (UART2_rx_int),
-
-//SPI0 (Flash)
-//declared under MEMORY
-.SPI0_QSPI      (SPI0_QSPI),
-
-//SPI1 (USB0/CH376T)
-.SPI1_clk       (SPI1_clk),
-.SPI1_cs        (SPI1_cs),
-.SPI1_mosi      (SPI1_mosi),
-.SPI1_miso      (SPI1_miso),
-.SPI1_nint      (SPI1_nint_stable),
-
-//SPI2 (USB1/CH376T)
-.SPI2_clk       (SPI2_clk),
-.SPI2_cs        (SPI2_cs),
-.SPI2_mosi      (SPI2_mosi),
-.SPI2_miso      (SPI2_miso),
-.SPI2_nint      (SPI2_nint_stable),
-
-//SPI3 (W5500)
-.SPI3_clk       (SPI3_clk),
-.SPI3_cs        (SPI3_cs),
-.SPI3_mosi      (SPI3_mosi),
-.SPI3_miso      (SPI3_miso),
-.SPI3_int       (SPI3_int_stable),
-
-//SPI4 (EXT/GP)
-.SPI4_clk       (SPI4_clk),
-.SPI4_cs        (SPI4_cs),
-.SPI4_mosi      (SPI4_mosi),
-.SPI4_miso      (SPI4_miso),
-.SPI4_GP        (SPI4_gp_stable),
-
-//GPIO (Separated GPI and GPO until GPIO module is implemented)
-.GPI        (GPI[3:0]),
-.GPO        (GPO[3:0]),
-
-//OStimers
-.OST1_int   (OST1_int),
-.OST2_int   (OST2_int),
-.OST3_int   (OST3_int),
-
-//SNESpad
-/*
-.SNES_clk   (),
-.SNES_latch (),
-.SNES_data  (),
-*/
-
-//PS/2
-.PS2_clk    (PS2_clk),
-.PS2_data   (PS2_data),
-.PS2_int    (PS2_int), //Scan code ready signal
-
-.halfRes(halfRes),
-
-//Boot mode
-.boot_mode  (boot_mode_stable)
+.bus_done       (bus_done)
 );
 
-
-//------------L2 Cache--------------
-//CPU bus
-wire [23:0]      l2_addr;  // address to write or to start reading from
-wire [31:0]      l2_data;  // data to write
-wire             l2_we;    // write enable
-wire             l2_start; // start trigger
-wire [31:0]      l2_q;     // memory output
-wire             l2_done;  // output ready
-
-L2cache l2cache(
-.clk            (clk_SDRAM),
-.reset          (reset),
-
-// CPU bus
-.l2_addr       (l2_addr),
-.l2_data       (l2_data),
-.l2_we         (l2_we),
-.l2_start      (l2_start),
-.l2_q          (l2_q),
-.l2_done       (l2_done),
-
-// sdram bus
-.sdc_addr       (sdc_addr),
-.sdc_data       (sdc_data),
-.sdc_we         (sdc_we),
-.sdc_start      (sdc_start),
-.sdc_q          (sdc_q),
-.sdc_done       (sdc_done)
-);
-
-
 //---------------CPU----------------
-//CPU I/O
-wire [26:0] PC;
-
 CPU cpu(
 .clk            (clk),
 .reset          (reset),
@@ -678,93 +57,7 @@ CPU cpu(
 .bus_q          (bus_q),
 .bus_done       (bus_done),
 
-// sdram bus
-.sdc_addr       (l2_addr),
-.sdc_data       (l2_data),
-.sdc_we         (l2_we),
-.sdc_start      (l2_start),
-.sdc_q          (l2_q),
-.sdc_done       (l2_done),
-
-.int1           (OST1_int),            //OStimer1
-.int2           (OST2_int),            //OStimer2
-.int3           (UART0_rx_int),        //UART0 rx (MAIN)
-.int4           (frameDrawn_stable),   //GPU Frame Drawn
-.int5           (OST3_int),            //OStimer3
-.int6           (PS2_int),             //PS/2 scancode ready
-.int7           (1'b0),                //UART1 rx (APU)
-.int8           (UART2_rx_int),        //UART2 rx (EXT)
-
-.PC             (PC)
-);
-
-
-//-----------STATUS LEDS-----------
-assign led_Booted = (PC >= 27'hC02522 | reset);
-assign led_HDMI = (~selectOutput | reset);
-assign led_QSPI = (~SPI0_QSPI | reset);
-
-LEDvisualizer #(.MIN_CLK(100000))
-LEDvisUSB0
-(
-.clk(clk),
-.reset(reset),
-.activity(~SPI1_cs),
-.LED(led_USB0)
-);
-
-LEDvisualizer #(.MIN_CLK(100000))
-LEDvisUSB1
-(
-.clk(clk),
-.reset(reset),
-.activity(~SPI2_cs),
-.LED(led_USB1)
-);
-
-LEDvisualizer #(.MIN_CLK(100000))
-LEDvisEth
-(
-.clk(clk),
-.reset(reset),
-.activity(~SPI3_cs),
-.LED(led_Eth)
-);
-
-LEDvisualizer #(.MIN_CLK(100000))
-LEDvisPS2
-(
-.clk(clk),
-.reset(reset),
-.activity(PS2_int),
-.LED(led_PS2)
-);
-
-LEDvisualizer #(.MIN_CLK(100000))
-LEDvisFlash
-(
-.clk(clk),
-.reset(reset),
-.activity(~SPI0_cs),
-.LED(led_Flash)
-);
-
-LEDvisualizer #(.MIN_CLK(100000))
-LEDvisGPU
-(
-.clk(clk),
-.reset(reset),
-.activity(vram32_cpu_we|vram8_cpu_we|vramSPR_cpu_we|vramPX_cpu_we),
-.LED(led_GPU)
-);
-
-LEDvisualizer #(.MIN_CLK(100000))
-LEDvisI2S
-(
-.clk(clk),
-.reset(reset),
-.activity(I2S_SDIN),
-.LED(led_I2S)
+.led            (led)
 );
 
 endmodule

Verilog/modules/Memory/MemoryUnit.v

@@ -12,838 +12,50 @@ module MemoryUnit(
     input           bus_we,
     input           bus_start,
     output [31:0]   bus_q,
-    output reg      bus_done = 1'b0,
-
-    /********
-    * MEMORY
-    ********/
-
-    //SPI Flash / SPI0
-    inout           SPIflash_data, SPIflash_q, SPIflash_wp, SPIflash_hold,
-    output          SPIflash_cs,
-    output          SPIflash_clk,
-
-    //VRAM32 cpu port
-    output [31:0]   VRAM32_cpu_d,
-    output [13:0]   VRAM32_cpu_addr,
-    output          VRAM32_cpu_we,
-    input  [31:0]   VRAM32_cpu_q,
-
-    //VRAM8 cpu port
-    output [7:0]    VRAM8_cpu_d,
-    output [13:0]   VRAM8_cpu_addr,
-    output          VRAM8_cpu_we,
-    input  [7:0]    VRAM8_cpu_q,
-
-    //VRAMspr cpu port
-    output [8:0]    VRAMspr_cpu_d,
-    output [13:0]   VRAMspr_cpu_addr,
-    output          VRAMspr_cpu_we,
-    input  [8:0]    VRAMspr_cpu_q,
-
-    //VRAMpx cpu port
-    output [23:0]   VRAMpx_cpu_d,
-    output [16:0]   VRAMpx_cpu_addr,
-    output          VRAMpx_cpu_we,
-    input  [23:0]   VRAMpx_cpu_q,
-
-    //ROM
-    output [8:0]    ROM_addr,
-    input  [31:0]   ROM_q,
-
-    /********
-    * I/O
-    ********/
-
-    //UART0 (Main USB)
-    input           UART0_in,
-    output          UART0_out,
-    output          UART0_rx_interrupt,
-
-    //UART1 (APU) DEPRECATED
-    //input           UART1_in,
-    //output          UART1_out,
-    //output          UART1_rx_interrupt,
-
-    //UART2 (GP)
-    input           UART2_in,
-    output          UART2_out,
-    output          UART2_rx_interrupt,
-
-    //SPI0 (Flash)
-    //declared under MEMORY
-    output          SPI0_QSPI,
-
-    //SPI1 (USB0/CH376T)
-    output          SPI1_clk,
-    output reg      SPI1_cs = 1'b1,
-    output          SPI1_mosi,
-    input           SPI1_miso,
-    input           SPI1_nint,
-
-    //SPI2 (USB1/CH376T)
-    output          SPI2_clk,
-    output reg      SPI2_cs = 1'b1,
-    output          SPI2_mosi,
-    input           SPI2_miso,
-    input           SPI2_nint,
-
-    //SPI3 (W5500)
-    output          SPI3_clk,
-    output reg      SPI3_cs = 1'b1,
-    output          SPI3_mosi,
-    input           SPI3_miso,
-    input           SPI3_int,
-
-    //SPI4 (EXT/GP)
-    output          SPI4_clk,
-    output reg      SPI4_cs = 1'b1,
-    output          SPI4_mosi,
-    input           SPI4_miso,
-    input           SPI4_GP,
-
-    //GPIO (Separated GPI and GPO until GPIO module is implemented)
-    input [3:0]     GPI,
-    output reg [3:0]GPO = 4'd0,
-
-    //OStimers
-    output          OST1_int,
-    output          OST2_int,
-    output          OST3_int,
-
-    //PS/2
-    input           PS2_clk, PS2_data,
-    output          PS2_int,            //Scan code ready signal
-
-    output reg halfRes = 1'b0,
-
-    //Boot mode
-    input           boot_mode
-
-);
-
-// Address select parameters
-localparam 
-    A_SDRAM = 0,
-    A_FLASH = 1,
-    A_VRAM32 = 2,
-    A_VRAM8 = 3,
-    A_VRAMSPR = 4,
-    A_ROM = 5,
-    A_UART0RX = 6,
-    A_UART0TX = 7,
-    //A_UART1RX = 8,
-    //A_UART1TX = 9,
-    A_UART2RX = 10,
-    A_UART2TX = 11,
-    A_SPI0 = 12,
-    A_SPI0CS = 13,
-    A_SPI0EN = 14,
-    A_SPI1 = 15,
-    A_SPI1CS = 16,
-    A_SPI1NINT = 17,
-    A_SPI2 = 18,
-    A_SPI2CS = 19,
-    A_SPI2NINT = 20,
-    A_SPI3 = 21,
-    A_SPI3CS = 22,
-    A_SPI3INT = 23,
-    A_SPI4 = 24,
-    A_SPI4CS = 25,
-    A_SPI4GP = 26,
-    A_GPIO = 27,
-    A_GPIODIR = 28,
-    A_TIMER1VAL = 29,
-    A_TIMER1CTRL = 30,
-    A_TIMER2VAL = 31,
-    A_TIMER2CTRL = 32,
-    A_TIMER3VAL = 33,
-    A_TIMER3CTRL = 34,
-    //A_SNESPAD = 35,
-    A_PS2 = 36,
-    A_BOOTMODE = 37,
-    A_VRAMPX = 38,
-    A_FPDIVWA = 39,
-    A_FPDIVSTART = 40,
-    A_IDIVWA = 41,
-    A_IDIVSTARTS = 42,
-    A_IDIVSTARTU = 43,
-    A_IDIVMODS = 44,
-    A_IDIVMODU = 45,
-    A_HALFRES = 46,
-    A_MILLIS = 47;
-
-//------------
-//SPI0 (flash) TODO: move this to a separate module
-//------------
-
-//SPIreader
-wire [23:0] SPIflashReader_addr;            //address of flash (32 bit)
-wire        SPIflashReader_start;           //start signal for SPIreader
-wire        SPIflashReader_cs;              //cs
-wire [31:0] SPIflashReader_q;               //data out
-wire        SPIflashReader_initDone;        //initdone of SPIreader
-wire        SPIflashReader_recvDone;        //recvdone of SPIreader TODO might change this to busy
-wire        SPIflashReader_reset;           //reset SPIreader
-wire        SPIflashReader_write;           //output mode of inout pins (high when writing to SPI flash)
-wire        SPIflashReader_clk;             //clk for spi flash
-
-wire io0_out, io1_out, io2_out, io3_out;    //d, q wp, hold output
-wire io0_in,  io1_in,  io2_in,  io3_in;     //d, q wp, hold input
-
-SPIreader sreader (
-.clk        (clk),
-.reset      (SPIflashReader_reset),
-.cs         (SPIflashReader_cs),
-.address    (SPIflashReader_addr),
-.instr      (SPIflashReader_q),
-.start      (SPIflashReader_start),
-.initDone   (SPIflashReader_initDone),
-.recvDone   (SPIflashReader_recvDone),
-.write      (SPIflashReader_write),
-.spi_clk    (SPIflashReader_clk),
-.io0_out    (io0_out),
-.io1_out    (io1_out),
-.io2_out    (io2_out),
-.io3_out    (io3_out),
-.io0_in     (io0_in),
-.io1_in     (io1_in),
-.io2_in     (io2_in),
-.io3_in     (io3_in)
-);
-
-//SPI0 (flash)
-wire SPI0_clk;
-wire SPI0_mosi;
-reg  SPI0_cs = 1'b1;
-reg  SPI0_enable = 1'b0; //high enables SPI0 and disables SPIreader
-wire SPI0_start;
-wire [7:0] SPI0_in;
-wire [7:0] SPI0_out;
-wire SPI0_done;
-
-assign SPI0_QSPI = ~SPI0_enable;
-
-SimpleSPI #(
-.CLKS_PER_HALF_BIT(1))
-SPI0(
-.clk        (clk),
-.reset      (reset),
-.in_byte    (SPI0_in),
-.start      (SPI0_start),
-.done       (SPI0_done),
-.out_byte   (SPI0_out),
-.spi_clk    (SPI0_clk),
-.miso       (SPIflash_q),
-.mosi       (SPI0_mosi)
-);
-
-//Tri-state signals
-wire SPIcombined_d, SPIcombined_q, SPIcombined_wp, SPIcombined_hold, SPIcombined_OutputEnable;
-
-assign SPIflash_clk             = (SPI0_enable) ? SPI0_clk  : SPIflashReader_clk;
-assign SPIflash_cs              = (SPI0_enable) ? SPI0_cs   : SPIflashReader_cs;
-assign SPIflashReader_reset     = (SPI0_enable) ? 1'b1      : reset;
-
-assign SPIcombined_d            = (SPI0_enable) ? SPI0_mosi : io0_out;
-assign SPIcombined_q            = (SPI0_enable) ? 1'bz      : io1_out;
-assign SPIcombined_wp           = (SPI0_enable) ? 1'b1      : io2_out;
-assign SPIcombined_hold         = (SPI0_enable) ? 1'b1      : io3_out;
-assign SPIcombined_OutputEnable = (SPI0_enable) ? 1'b1      : SPIflashReader_write;
-
-assign SPIflash_data = (SPIcombined_OutputEnable) ? SPIcombined_d    : 1'bz;
-assign SPIflash_q    = (SPIcombined_OutputEnable) ? SPIcombined_q    : 1'bz;
-assign SPIflash_wp   = (SPIcombined_OutputEnable) ? SPIcombined_wp   : 1'bz;
-assign SPIflash_hold = (SPIcombined_OutputEnable) ? SPIcombined_hold : 1'bz;
-
-assign io0_in = (~SPIcombined_OutputEnable) ? SPIflash_data : 1'bz;
-assign io1_in = (~SPIcombined_OutputEnable) ? SPIflash_q    : 1'bz;
-assign io2_in = (~SPIcombined_OutputEnable) ? SPIflash_wp   : 1'bz;
-assign io3_in = (~SPIcombined_OutputEnable) ? SPIflash_hold : 1'bz;
-
-
-//------------
-//UART0
-//------------
-wire UART0_r_Tx_DV, UART0_w_Tx_Done;
-wire [7:0] UART0_r_Tx_Byte;
-
-UARTtx UART0_tx(
-.i_Clock    (clk),
-.reset      (reset),
-.i_Tx_DV    (UART0_r_Tx_DV),
-.i_Tx_Byte  (UART0_r_Tx_Byte),
-.o_Tx_Active(),
-.o_Tx_Serial(UART0_out),
-.o_Tx_Done  (UART0_w_Tx_Done)
-);
-
-wire [7:0] UART0_w_Rx_Byte;
-
-UARTrx UART0_rx(
-.i_Clock    (clk),
-.reset      (reset),
-.i_Rx_Serial(UART0_in),
-.o_Rx_DV    (UART0_rx_interrupt),
-.o_Rx_Byte  (UART0_w_Rx_Byte)
-);
-
-
-//------------
-//UART1
-//------------
-/*
-wire UART1_r_Tx_DV, UART1_w_Tx_Done;
-wire [7:0] UART1_r_Tx_Byte;
-
-UARTtx UART1_tx(
-.i_Clock    (clk),
-.reset      (reset),
-.i_Tx_DV    (UART1_r_Tx_DV),
-.i_Tx_Byte  (UART1_r_Tx_Byte),
-.o_Tx_Active(),
-.o_Tx_Serial(UART1_out),
-.o_Tx_Done  (UART1_w_Tx_Done)
-);
-
-wire [7:0] UART1_w_Rx_Byte;
-
-UARTrx UART1_rx(
-.i_Clock    (clk),
-.reset      (reset),
-.i_Rx_Serial(UART1_in),
-.o_Rx_DV    (UART1_rx_interrupt),
-.o_Rx_Byte  (UART1_w_Rx_Byte)
-);
-*/
-
-
-//------------
-//UART2
-//------------
-wire UART2_r_Tx_DV, UART2_w_Tx_Done;
-wire [7:0] UART2_r_Tx_Byte;
-
-UARTtx UART2_tx(
-.i_Clock    (clk),
-.reset      (reset),
-.i_Tx_DV    (UART2_r_Tx_DV),
-.i_Tx_Byte  (UART2_r_Tx_Byte),
-.o_Tx_Active(),
-.o_Tx_Serial(UART2_out),
-.o_Tx_Done  (UART2_w_Tx_Done)
-);
-
-wire [7:0] UART2_w_Rx_Byte;
-
-UARTrx UART2_rx(
-.i_Clock    (clk),
-.reset      (reset),
-.i_Rx_Serial(UART2_in),
-.o_Rx_DV    (UART2_rx_interrupt),
-.o_Rx_Byte  (UART2_w_Rx_Byte)
-);
-
-
-
-
-//------------
-//SPI1 (CH376T bottom)
-//------------
-wire SPI1_start;
-wire [7:0] SPI1_in;
-wire [7:0] SPI1_out;
-wire SPI1_done;
-
-SimpleSPI #(
-.CLKS_PER_HALF_BIT(2))
-SPI1(
-.clk        (clk),
-.reset      (reset),
-.in_byte    (SPI1_in),
-.start      (SPI1_start),
-.done       (SPI1_done),
-.out_byte   (SPI1_out),
-.spi_clk    (SPI1_clk),
-.miso       (SPI1_miso),
-.mosi       (SPI1_mosi)
-);
-
-
-//------------
-//SPI2 (CH376T top)
-//------------
-wire SPI2_start;
-wire [7:0] SPI2_in;
-wire [7:0] SPI2_out;
-wire SPI2_done;
-
-SimpleSPI #(
-.CLKS_PER_HALF_BIT(2))
-SPI2(
-.clk        (clk),
-.reset      (reset),
-.in_byte    (SPI2_in),
-.start      (SPI2_start),
-.done       (SPI2_done),
-.out_byte   (SPI2_out),
-.spi_clk    (SPI2_clk),
-.miso       (SPI2_miso),
-.mosi       (SPI2_mosi)
-);
-
-
-//------------
-//SPI3 (W5500)
-//------------
-wire SPI3_start;
-wire [7:0] SPI3_in;
-wire [7:0] SPI3_out;
-wire SPI3_done;
-
-SimpleSPI #(
-.CLKS_PER_HALF_BIT(1))
-SPI3(
-.clk        (clk),
-.reset      (reset),
-.in_byte    (SPI3_in),
-.start      (SPI3_start),
-.done       (SPI3_done),
-.out_byte   (SPI3_out),
-.spi_clk    (SPI3_clk),
-.miso       (SPI3_miso),
-.mosi       (SPI3_mosi)
-);
-
-
-//------------
-//SPI4 (EXT/GP)
-//------------
-wire SPI4_start;
-wire [7:0] SPI4_in;
-wire [7:0] SPI4_out;
-wire SPI4_done;
-
-SimpleSPI #(
-.CLKS_PER_HALF_BIT(2))
-SPI4(
-.clk        (clk),
-.reset      (reset),
-.in_byte    (SPI4_in),
-.start      (SPI4_start),
-.done       (SPI4_done),
-.out_byte   (SPI4_out),
-.spi_clk    (SPI4_clk),
-.miso       (SPI4_miso),
-.mosi       (SPI4_mosi)
-);
-
-
-
-
-//------------
-//GPIO
-//------------
-// TODO: To be implemented
-
-
-
-
-//------------
-//OS timer 1
-//------------
-wire OST1_trigger, OST1_set;
-wire [31:0] OST1_value;
-
-OStimer OST1(
-.clk        (clk),
-.reset      (reset),
-.timerValue (OST1_value),
-.setValue   (OST1_set),
-.trigger    (OST1_trigger),
-.interrupt  (OST1_int)
-);
-
-
-//------------
-//OS timer 2
-//------------
-wire OST2_trigger, OST2_set;
-wire [31:0] OST2_value;
-
-OStimer OST2(
-.clk        (clk),
-.reset      (reset),
-.timerValue (OST2_value),
-.setValue   (OST2_set),
-.trigger    (OST2_trigger),
-.interrupt  (OST2_int)
-);
-
-
-//------------
-//OS timer 3
-//------------
-wire OST3_trigger, OST3_set;
-wire [31:0] OST3_value;
-
-OStimer OST3(
-.clk        (clk),
-.reset      (reset),
-.timerValue (OST3_value),
-.setValue   (OST3_set),
-.trigger    (OST3_trigger),
-.interrupt  (OST3_int)
-);
-
-
-//------------
-//Millis counter
-//------------
-wire [31:0] millis;
-
-MillisCounter millisCounter(
-.clk        (clk),
-.reset      (reset),
-.millis     (millis)
-);
-
-//------------
-//SNES controller
-//------------
-/*
-wire [15:0] SNES_state;
-wire SNES_done;
-wire SNES_start;
-
-NESpadReader npr (
-.clk(clk),
-.reset(reset),
-.nesc(SNES_clk),
-.nesl(SNES_latch),
-.nesd(SNES_data),
-.nesState(SNES_state),
-.frame(SNES_start),
-.done(SNES_done)
-);*/
-
-
-
-
-//------------
-//PS/2 keyboard
-//------------
-wire [7:0] PS2_scanCode;
-
-Keyboard PS2Keyboard (
-.clk            (clk),
-.reset          (reset),
-.ps2d           (PS2_data),
-.ps2c           (PS2_clk),
-.rx_done_tick   (PS2_int),
-.rx_data        (PS2_scanCode)
-);
-
-
-wire [31:0] fpdiv_input;
-wire fpdiv_write_a;
-wire fpdiv_busy;
-wire fpdiv_start;
-
-wire [31:0] fpdiv_val;
-
-
-FPDivider fpdivider(
-.clk        (clk), 
-.rst        (reset),
-.start      (fpdiv_start),  // start calculation
-.write_a    (fpdiv_write_a),
-.busy       (fpdiv_busy),   // calculation in progress
-//.done       (fpdiv_done),   // calculation is complete (high for one tick)
-//.valid      (valid),  // result is valid
-//.dbz        (dbz),    // divide by zero
-//.ovf        (ovf),    // overflow
-.a_in       (bus_data),   // dividend (numerator)
-.b          (bus_data),   // divisor (denominator)
-.val        (fpdiv_val)  // result value: quotient
+    output reg      bus_done = 1'b0
 );
 
+reg bus_done_next = 1'b0;
 
 
-wire [31:0] idiv_input;
-wire idiv_write_a;
-wire idiv_ready;
-wire idiv_start;
-wire idiv_signed;
+//---------------------------SRAM---------------------------------
+//SRAM I/O
+wire        sram_cpu_clk;
+wire [11:0] sram_cpu_addr;
+wire [31:0] sram_cpu_d;
+wire        sram_cpu_we; 
+wire [31:0] sram_cpu_q;
 
-wire [31:0] idiv_q;
-wire [31:0] idiv_r;
+assign sram_cpu_addr = bus_addr;
+assign sram_cpu_d    = bus_data;
+assign sram_cpu_we   = bus_we;
 
+assign bus_q = sram_cpu_q;
 
-IDivider idivider(
-.clk        (clk), 
-.rst        (reset),
-.start      (idiv_start),  // start calculation
-.write_a    (idiv_write_a),
-.ready      (idiv_ready),   // !calculation in progress
-.flush      (1'b0),
-.signed_ope (idiv_signed), // signed or unsiged
-.a          (bus_data),   // dividend (numerator)
-.b          (bus_data),   // divisor (denominator)
-.quotient   (idiv_q),  // result value: quotient
-.remainder  (idiv_r)
+SRAM #(
+.WIDTH(32),
+.WORDS(4096),
+.ADDR_BITS(12),
+.LIST("/home/bart/Documents/FPGA/FPGC6/Verilog/memory/sram.list")
+)   sram(
+//CPU port
+.cpu_clk    (clk),
+.cpu_d      (sram_cpu_d),
+.cpu_addr   (sram_cpu_addr),
+.cpu_we     (sram_cpu_we),
+.cpu_q      (sram_cpu_q)
 );
 
 
-reg [31:0] bus_d_reg = 32'd0;
-
-//----
-//MEMORY
-//----
-
-//SPI FLASH MEMORY
-assign SPIflashReader_addr  = bus_addr - 27'h800000;
-assign SPIflashReader_start = bus_addr >= 27'h800000 && bus_addr < 27'hC00000 && bus_start;
-
-//VRAM32
-assign VRAM32_cpu_addr      = bus_addr - 27'hC00000;
-assign VRAM32_cpu_d         = bus_d_reg;
-assign VRAM32_cpu_we        = bus_addr >= 27'hC00000 && bus_addr < 27'hC00420 && bus_we;
-
-//VRAM8
-assign VRAM8_cpu_addr       = bus_addr - 27'hC00420;
-assign VRAM8_cpu_d          = bus_data;
-assign VRAM8_cpu_we         = bus_addr >= 27'hC00420 && bus_addr < 27'hC02422 && bus_we;
-
-//VRAMspr
-assign VRAMspr_cpu_addr     = bus_addr - 27'hC02422;
-assign VRAMspr_cpu_d        = bus_data;
-assign VRAMspr_cpu_we       = bus_addr >= 27'hC02422 && bus_addr < 27'hC02522 && bus_we;
-
-//VRAMpx
-assign VRAMpx_cpu_addr     = bus_addr - 27'hD00000;
-assign VRAMpx_cpu_d        = bus_data;
-assign VRAMpx_cpu_we       = bus_addr >= 27'hD00000 && bus_addr < 27'hD12C00 && bus_we;
-
-//ROM
-assign ROM_addr             = bus_addr - 27'hC02522;
-
-
-//----
-//I/O
-//----
-
-//UART
-assign UART0_r_Tx_DV    = bus_addr == 27'hC02723 && bus_we && bus_start;
-assign UART0_r_Tx_Byte  = bus_data;
-
-
-//assign UART1_r_Tx_DV    = bus_addr == 27'hC02725 && bus_we && bus_start;
-//assign UART1_r_Tx_Byte  = bus_data;
-
-assign UART2_r_Tx_DV    = bus_addr == 27'hC02727 && bus_we && bus_start;
-assign UART2_r_Tx_Byte  = bus_data;
-
-//SPI
-assign SPI0_in          = bus_data;
-assign SPI0_start       = bus_addr == 27'hC02728 && bus_we && bus_start;
-
-assign SPI1_in          = bus_data;
-assign SPI1_start       = bus_addr == 27'hC0272B && bus_we && bus_start;
-
-assign SPI2_in          = bus_data;
-assign SPI2_start       = bus_addr == 27'hC0272E && bus_we && bus_start;
-
-assign SPI3_in          = bus_data;
-assign SPI3_start       = bus_addr == 27'hC02731 && bus_we && bus_start;
-
-assign SPI4_in          = bus_data;
-assign SPI4_start       = bus_addr == 27'hC02734 && bus_we && bus_start;
-
-//OS Timers
-assign OST1_value       = bus_data;
-assign OST1_set         = (bus_addr == 27'hC02739 && bus_we);
-assign OST1_trigger     = (bus_addr == 27'hC0273A && bus_we);
-
-assign OST2_value       = bus_data;
-assign OST2_set         = (bus_addr == 27'hC0273B && bus_we);
-assign OST2_trigger     = (bus_addr == 27'hC0273C && bus_we);
-
-assign OST3_value       = bus_data;
-assign OST3_set         = (bus_addr == 27'hC0273D && bus_we);
-assign OST3_trigger     = (bus_addr == 27'hC0273E && bus_we);
-
-//SNES
-//assign SNES_start       = bus_addr == 27'hC0273F && bus_start;
-
-//Divider
-assign fpdiv_write_a      = (bus_addr == 27'hC02742 && bus_we);
-assign fpdiv_start        = (bus_addr == 27'hC02743 && bus_we);
-
-assign idiv_write_a      = (bus_addr == 27'hC02744 && bus_we);
-assign idiv_start        = (
-                            (bus_addr == 27'hC02745 ||
-                                bus_addr == 27'hC02746 || 
-                                bus_addr == 27'hC02747 || 
-                                bus_addr == 27'hC02748
-                            ) 
-                            && bus_we
-                           );
-assign idiv_signed       = ((bus_addr == 27'hC02745 || bus_addr == 27'hC02747) && bus_we);
-
-
-reg [5:0] a_sel;
-
-// Address selection
-always @(bus_addr)
-begin
-    a_sel = 6'd0;
-    if (bus_addr < 27'h800000) a_sel = A_SDRAM;
-    if (bus_addr >= 27'h800000 && bus_addr < 27'hC00000) a_sel = A_FLASH;
-    if (bus_addr >= 27'hC00000 && bus_addr < 27'hC00420) a_sel = A_VRAM32;
-    if (bus_addr >= 27'hC00420 && bus_addr < 27'hC02422) a_sel = A_VRAM8;
-    if (bus_addr >= 27'hC02422 && bus_addr < 27'hC02522) a_sel = A_VRAMSPR;
-    if (bus_addr >= 27'hC02522 && bus_addr < 27'hC02722) a_sel = A_ROM;
-    if (bus_addr == 27'hC02722) a_sel = A_UART0RX;
-    if (bus_addr == 27'hC02723) a_sel = A_UART0TX;
-    //if (bus_addr == 27'hC02724) a_sel = A_UART1RX;
-    //if (bus_addr == 27'hC02725) a_sel = A_UART1TX;
-    if (bus_addr == 27'hC02726) a_sel = A_UART2RX;
-    if (bus_addr == 27'hC02727) a_sel = A_UART2TX;
-    if (bus_addr == 27'hC02728) a_sel = A_SPI0;
-    if (bus_addr == 27'hC02729) a_sel = A_SPI0CS;
-    if (bus_addr == 27'hC0272A) a_sel = A_SPI0EN;
-    if (bus_addr == 27'hC0272B) a_sel = A_SPI1;
-    if (bus_addr == 27'hC0272C) a_sel = A_SPI1CS;
-    if (bus_addr == 27'hC0272D) a_sel = A_SPI1NINT;
-    if (bus_addr == 27'hC0272E) a_sel = A_SPI2;
-    if (bus_addr == 27'hC0272F) a_sel = A_SPI2CS;
-    if (bus_addr == 27'hC02730) a_sel = A_SPI2NINT;
-    if (bus_addr == 27'hC02731) a_sel = A_SPI3;
-    if (bus_addr == 27'hC02732) a_sel = A_SPI3CS;
-    if (bus_addr == 27'hC02733) a_sel = A_SPI3INT;
-    if (bus_addr == 27'hC02734) a_sel = A_SPI4;
-    if (bus_addr == 27'hC02735) a_sel = A_SPI4CS;
-    if (bus_addr == 27'hC02736) a_sel = A_SPI4GP;
-    if (bus_addr == 27'hC02737) a_sel = A_GPIO;
-    if (bus_addr == 27'hC02738) a_sel = A_GPIODIR;
-    if (bus_addr == 27'hC02739) a_sel = A_TIMER1VAL;
-    if (bus_addr == 27'hC0273A) a_sel = A_TIMER1CTRL;
-    if (bus_addr == 27'hC0273B) a_sel = A_TIMER2VAL;
-    if (bus_addr == 27'hC0273C) a_sel = A_TIMER2CTRL;
-    if (bus_addr == 27'hC0273D) a_sel = A_TIMER3VAL;
-    if (bus_addr == 27'hC0273E) a_sel = A_TIMER3CTRL;
-    //if (bus_addr == 27'hC0273F) a_sel = A_SNESPAD;
-    if (bus_addr == 27'hC02740) a_sel = A_PS2;
-    if (bus_addr == 27'hC02741) a_sel = A_BOOTMODE;
-    if (bus_addr == 27'hC02742) a_sel = A_FPDIVWA;
-    if (bus_addr == 27'hC02743) a_sel = A_FPDIVSTART;
-    if (bus_addr == 27'hC02744) a_sel = A_IDIVWA;
-    if (bus_addr == 27'hC02745) a_sel = A_IDIVSTARTS;
-    if (bus_addr == 27'hC02746) a_sel = A_IDIVSTARTU;
-    if (bus_addr == 27'hC02747) a_sel = A_IDIVMODS;
-    if (bus_addr == 27'hC02748) a_sel = A_IDIVMODU;
-    if (bus_addr == 27'hC02749) a_sel = A_HALFRES;
-    if (bus_addr == 27'hC0274A) a_sel = A_MILLIS;
-    if (bus_addr >= 27'hD00000 && bus_addr < 27'hD12C00) a_sel = A_VRAMPX;
-end
-
-reg [31:0] bus_q_wire;
-reg [31:0] bus_q_wire_reg = 32'd0;
-always @(*)
-begin
-    case (a_sel)
-        A_SDRAM:        bus_q_wire = 32'd0; //sd_q; sdram is removed now!
-        A_FLASH:        bus_q_wire = SPIflashReader_q;
-        A_VRAM32:       bus_q_wire = VRAM32_cpu_q;
-        A_VRAM8:        bus_q_wire = VRAM8_cpu_q;
-        A_VRAMSPR:      bus_q_wire = VRAMspr_cpu_q;
-        A_ROM:          bus_q_wire = ROM_q;
-        A_UART0RX:      bus_q_wire = UART0_w_Rx_Byte;
-        //A_UART0TX:      bus_q_wire = 
-        //A_UART1RX:      bus_q_wire = UART1_w_Rx_Byte;
-        //A_UART1TX:      bus_q_wire = 
-        A_UART2RX:      bus_q_wire = UART2_w_Rx_Byte;
-        //A_UART2TX:      bus_q_wire = 
-        A_SPI0:         bus_q_wire = SPI0_out;
-        A_SPI0CS:       bus_q_wire = SPI0_cs;
-        A_SPI0EN:       bus_q_wire = SPI0_enable;
-        A_SPI1:         bus_q_wire = SPI1_out;
-        A_SPI1CS:       bus_q_wire = SPI1_cs;
-        A_SPI1NINT:     bus_q_wire = SPI1_nint;
-        A_SPI2:         bus_q_wire = SPI2_out;
-        A_SPI2CS:       bus_q_wire = SPI2_cs;
-        A_SPI2NINT:     bus_q_wire = SPI2_nint;
-        A_SPI3:         bus_q_wire = SPI3_out;
-        A_SPI3CS:       bus_q_wire = SPI3_cs;
-        A_SPI3INT:      bus_q_wire = SPI3_int;
-        A_SPI4:         bus_q_wire = SPI4_out;
-        A_SPI4CS:       bus_q_wire = SPI4_cs;
-        A_SPI4GP:       bus_q_wire = SPI4_GP;
-        A_GPIO:         bus_q_wire = {24'd0, GPO, GPI};
-        //A_GPIODIR:      bus_q_wire = 
-        //A_TIMER1VAL:    bus_q_wire = 
-        //A_TIMER1CTRL:   bus_q_wire = 
-        //A_TIMER2VAL:    bus_q_wire = 
-        //A_TIMER2CTRL:   bus_q_wire = 
-        //A_TIMER3VAL:    bus_q_wire = 
-        //A_TIMER3CTRL:   bus_q_wire = 
-        //A_SNESPAD:      bus_q_wire = {16'd0, SNES_state};
-        A_PS2:          bus_q_wire = {24'd0, PS2_scanCode};
-        A_BOOTMODE:     bus_q_wire = {31'd0, boot_mode};
-        A_VRAMPX:       bus_q_wire = VRAMpx_cpu_q;
-        A_FPDIVSTART:   bus_q_wire = fpdiv_val;
-        A_IDIVSTARTS:   bus_q_wire = idiv_q;
-        A_IDIVSTARTU:   bus_q_wire = idiv_q;
-        A_IDIVMODS:     bus_q_wire = idiv_r;
-        A_IDIVMODU:     bus_q_wire = idiv_r;
-        A_MILLIS:       bus_q_wire = millis;
-        default:        bus_q_wire = 32'd0;
-    endcase
-end
-
-always @(posedge clk)
-begin
-    if (reset)
-    begin
-        bus_q_wire_reg <= 32'd0;
-        bus_d_reg <= 32'd0;
-    end
-    else
-    begin
-        bus_d_reg <= bus_data; // latch for copy instructions to SRAM/regs
-
-        // latch output
-        if (bus_done || bus_done_next || SPIflashReader_recvDone) // TODO: Should probably add more ready statements here
-            bus_q_wire_reg <= bus_q_wire;
-    end
-end
-
-reg bus_done_next = 1'b0;
-
-assign bus_q =      (a_sel == A_ROM) ? ROM_q: // safe because ROM cannot be the destination of a copy instruction
-                    bus_q_wire_reg;
-
-
 always @(posedge clk)
 begin
     if (reset)
     begin
-        GPO         <= 4'd0;
-        SPI0_enable <= 1'b0;
         bus_done <= 1'b0;
         bus_done_next <= 1'b0;
-        SPI0_cs     <= 1'b1;
-        SPI1_cs     <= 1'b1;
-        SPI2_cs     <= 1'b1;
-        SPI3_cs     <= 1'b1;
-        SPI4_cs     <= 1'b1;
-        //TODO: add reset
-        
     end
     else
     begin
-
         if (bus_done_next)
         begin
             bus_done_next <= 1'b0;
@@ -852,188 +64,13 @@ begin
         else
         begin
             bus_done <= 1'b0;
-        end
-
-        if (bus_start)
-        begin
-            case (a_sel)
-                A_SDRAM:
-                begin
-                    bus_done <= 1'b0; // this is to make sure bus_done from MU will never be used when SDRAM access
-                end
-                A_FLASH:
-                begin
-                    if (SPIflashReader_recvDone || SPI0_enable)
-                        bus_done <= 1'b1;
-                end
-
-                A_UART0TX:
-                begin
-                    if (UART0_w_Tx_Done)
-                        bus_done <= 1'b1;
-                end
 
-                /*
-                A_UART1TX:
-                begin
-                    if (UART1_w_Tx_Done)
-                        bus_done <= 1'b1;
-                end
-                */
-
-                A_UART2TX:
-                begin
-                    if (UART2_w_Tx_Done)
-                        bus_done <= 1'b1;
-                end
-
-                A_SPI0:
-                begin
-                    if (SPI0_done)
-                        if (!bus_done_next) bus_done_next <= 1'b1;
-                end
-
-                A_SPI0CS:
-                begin
-                    if (bus_we)
-                    begin
-                        SPI0_cs <= bus_data[0];
-                    end
-                    if (!bus_done_next) bus_done_next <= 1'b1;
-                end
-
-                A_SPI0EN:
-                begin
-                    if (bus_we)
-                    begin
-                        SPI0_enable <= bus_data[0];
-                    end
-                    if (!bus_done_next) bus_done_next <= 1'b1;
-                end
-
-                A_SPI1:
-                begin
-                    if (SPI1_done)
-                        if (!bus_done_next) bus_done_next <= 1'b1;
-                end
-
-                A_SPI1CS:
-                begin
-                    if (bus_we)
-                    begin
-                        SPI1_cs <= bus_data[0];
-                    end
-                    if (!bus_done_next) bus_done_next <= 1'b1;
-                end
-
-                A_SPI2:
-                begin
-                    if (SPI2_done)
-                        if (!bus_done_next) bus_done_next <= 1'b1;
-                end
-
-                A_SPI2CS:
-                begin
-                    if (bus_we)
-                    begin
-                        SPI2_cs <= bus_data[0];
-                    end
-                    if (!bus_done_next) bus_done_next <= 1'b1;
-                end
-
-                A_SPI3:
-                begin
-                    if (SPI3_done)
-                        if (!bus_done_next) bus_done_next <= 1'b1;
-                end
-
-                A_SPI3CS:
-                begin
-                    if (bus_we)
-                    begin
-                        SPI3_cs <= bus_data[0];
-                    end
-                    if (!bus_done_next) bus_done_next <= 1'b1;
-                end
-
-                A_SPI4:
-                begin
-                    if (SPI4_done)
-                        if (!bus_done_next) bus_done_next <= 1'b1;
-                end
-
-                A_SPI4CS:
-                begin
-                    if (bus_we)
-                    begin
-                        SPI4_cs <= bus_data[0];
-                    end
-                    if (!bus_done_next) bus_done_next <= 1'b1;
-                end
-
-                A_GPIO:
-                begin
-                    if (bus_we)
-                    begin
-                        GPO <= bus_data[7:4];
-                    end
-                        if (!bus_done_next) bus_done_next <= 1'b1;
-                end
-
-                /*
-                A_SNESPAD:
-                begin
-                    if (SNES_done)
-                        bus_done <= 1'b1;
-                end
-                */
-
-                A_VRAM8, A_VRAM32, A_VRAMSPR, A_VRAMPX:
-                begin
-                    if (bus_we)
-                        bus_done <= 1'b1;
-                    else
-                        if (!bus_done_next) bus_done_next <= 1'b1;
-                end
-
-                A_ROM:
-                begin
-                    bus_done <= 1'b1;
-                end
-
-                A_FPDIVSTART:
-                begin
-                    if (!fpdiv_busy)
-                        if (!bus_done_next) bus_done_next <= 1'b1;
-                end
-
-                A_IDIVSTARTS, A_IDIVSTARTU, A_IDIVMODS, A_IDIVMODU:
-                begin
-                    if (idiv_ready)
-                        if (!bus_done_next) bus_done_next <= 1'b1;
-                end
-
-                A_HALFRES:
-                begin
-                    if (bus_we)
-                    begin
-                        halfRes <= bus_data[0];
-                    end
-                        if (!bus_done_next) bus_done_next <= 1'b1;
-                end
-
-                default:
-                begin
-                    if (!bus_done_next) bus_done_next <= 1'b1;
-                end
-
-            endcase
-
-                
+            if (bus_start)
+            begin
+                if (!bus_done_next) bus_done_next <= 1'b1;
+            end
         end
-
     end
-
 end
 
 endmodule

Verilog/modules/Memory/SRAM.v

@@ -0,0 +1,38 @@
+/*
+* SRAM implementation
+*/
+module SRAM
+#(
+    parameter WIDTH = 32,
+    parameter WORDS = 4096,
+    parameter ADDR_BITS = 12,
+    parameter LIST  = "/home/bart/Documents/FPGA/FPGC6/Verilog/memory/sram.list"
+) 
+(
+  input                   cpu_clk,        
+  input      [WIDTH-1:0]  cpu_d,
+  input      [ADDR_BITS-1:0]       cpu_addr,
+  input                   cpu_we,
+  output reg [WIDTH-1:0]  cpu_q
+);
+
+reg [WIDTH-1:0] ram [0:WORDS-1]; //basically the memory cells
+
+//cpu port
+always @(posedge cpu_clk) 
+begin
+  cpu_q <= ram[cpu_addr];
+  if (cpu_we)
+  begin
+    cpu_q         <= cpu_d;
+    ram[cpu_addr] <= cpu_d;
+  end
+end
+
+//initialize VRAM
+initial 
+begin
+  $readmemb(LIST, ram);
+end
+    
+endmodule

Verilog/output/FPGC.gtkw

@@ -1,315 +1,75 @@
 [*]
-[*] GTKWave Analyzer v3.3.107 (w)1999-2020 BSI
-[*] Sat Sep  2 21:10:16 2023
+[*] GTKWave Analyzer v3.3.116 (w)1999-2023 BSI
+[*] Sun May 19 13:59:52 2024
 [*]
 [dumpfile] "/home/bart/Documents/FPGA/FPGC6/Verilog/output/wave.vcd"
-[dumpfile_mtime] "Sat Sep  2 16:09:11 2023"
-[dumpfile_size] 46133170
+[dumpfile_mtime] "Sun May 19 13:56:54 2024"
+[dumpfile_size] 757561
 [savefile] "/home/bart/Documents/FPGA/FPGC6/Verilog/output/FPGC.gtkw"
-[timestart] 25540000
-[size] 1920 1054
+[timestart] 0
+[size] 2560 1361
 [pos] -1 -1
-*-21.666576 1263700 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-5.400000 121 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] FPGC_tb.
 [treeopen] FPGC_tb.fpgc.
-[treeopen] FPGC_tb.fpgc.cpu.arbiter.
-[sst_width] 227
-[signals_width] 366
+[treeopen] FPGC_tb.fpgc.cpu.
+[sst_width] 278
+[signals_width] 417
 [sst_expanded] 1
-[sst_vpaned_height] 494
+[sst_vpaned_height] 420
 @28
-FPGC_tb.fpgc.clk
-@22
-FPGC_tb.fpgc.cpu.PC[26:0]
+FPGC_tb.clk
+FPGC_tb.fpgc.reset
+FPGC_tb.led
 @200
 -
--
--Arbiter
--
-@22
-FPGC_tb.fpgc.cpu.arbiter.addr_a[31:0]
-FPGC_tb.fpgc.cpu.arbiter.data_a[31:0]
-@28
-FPGC_tb.fpgc.cpu.arbiter.we_a
-FPGC_tb.fpgc.cpu.arbiter.start_a
-FPGC_tb.fpgc.cpu.arbiter.done_a
-@22
-FPGC_tb.fpgc.cpu.arbiter.q[31:0]
-@200
--
--
-@22
-FPGC_tb.fpgc.cpu.arbiter.addr_b[31:0]
-FPGC_tb.fpgc.cpu.arbiter.data_b[31:0]
-@28
-FPGC_tb.fpgc.cpu.arbiter.we_b
-FPGC_tb.fpgc.cpu.arbiter.start_b
-FPGC_tb.fpgc.cpu.arbiter.done_b
-@22
-FPGC_tb.fpgc.cpu.arbiter.q[31:0]
-@200
--
--
-@22
-FPGC_tb.fpgc.cpu.arbiter.bus_addr[26:0]
-FPGC_tb.fpgc.cpu.arbiter.bus_data[31:0]
-@28
-FPGC_tb.fpgc.cpu.arbiter.bus_we
-FPGC_tb.fpgc.cpu.arbiter.bus_start
-@29
-FPGC_tb.fpgc.cpu.arbiter.bus_done
-@200
--
--
-@24
-FPGC_tb.fpgc.cpu.arbiter.state[2:0]
-@200
--
--
--
--
--
--
-@22
-FPGC_tb.fpgc.cpu.arbiter_bus_addr[26:0]
-FPGC_tb.fpgc.cpu.arbiter_bus_data[31:0]
-@28
-FPGC_tb.fpgc.cpu.arbiter_bus_start
-FPGC_tb.fpgc.cpu.arbiter_bus_we
-@22
-FPGC_tb.fpgc.cpu.arbiter_bus_q[31:0]
-@28
-FPGC_tb.fpgc.cpu.arbiter_bus_done
-@200
--
-@22
-FPGC_tb.fpgc.cpu.bus_addr[26:0]
-FPGC_tb.fpgc.cpu.bus_data[31:0]
-@28
-FPGC_tb.fpgc.cpu.bus_we
-FPGC_tb.fpgc.cpu.bus_start
-@22
-FPGC_tb.fpgc.cpu.bus_q[31:0]
-@28
-FPGC_tb.fpgc.cpu.bus_done
-@200
--
-@22
-FPGC_tb.fpgc.cpu.sdc_addr[23:0]
-FPGC_tb.fpgc.cpu.sdc_data[31:0]
-@28
-FPGC_tb.fpgc.cpu.sdc_we
-FPGC_tb.fpgc.cpu.sdc_start
-@22
-FPGC_tb.fpgc.cpu.sdc_q[31:0]
-@28
-FPGC_tb.fpgc.cpu.sdc_done
-@200
--
--SDRAMcontroller
-@24
-FPGC_tb.fpgc.sdramcontroller.sdc_addr[23:0]
-@22
-FPGC_tb.fpgc.sdramcontroller.sdc_data[31:0]
-@28
-FPGC_tb.fpgc.sdramcontroller.sdc_we
-FPGC_tb.fpgc.sdramcontroller.sdc_start
-FPGC_tb.fpgc.sdramcontroller.sdc_done
-@24
-FPGC_tb.fpgc.sdramcontroller.state[4:0]
-@28
-FPGC_tb.fpgc.sdramcontroller.is_refreshing
-@22
-FPGC_tb.fpgc.sdramcontroller.sdc_q[31:0]
-@200
--
--
-@22
-FPGC_tb.fpgc.sdramcontroller.SDRAM_A[12:0]
-@28
-FPGC_tb.fpgc.sdramcontroller.SDRAM_BA[1:0]
-FPGC_tb.fpgc.sdramcontroller.SDRAM_CASn
-FPGC_tb.fpgc.sdramcontroller.SDRAM_CKE
-@22
-FPGC_tb.fpgc.sdramcontroller.SDRAM_CMD[3:0]
-@28
-FPGC_tb.fpgc.sdramcontroller.SDRAM_CSn
-@22
-FPGC_tb.fpgc.sdramcontroller.SDRAM_DATA[31:0]
-FPGC_tb.fpgc.sdramcontroller.SDRAM_DQM[3:0]
-FPGC_tb.fpgc.sdramcontroller.SDRAM_DQ[31:0]
-@28
-FPGC_tb.fpgc.sdramcontroller.SDRAM_DQ_OE
-@22
-FPGC_tb.fpgc.sdramcontroller.SDRAM_Q[31:0]
-@28
-FPGC_tb.fpgc.sdramcontroller.SDRAM_RASn
-FPGC_tb.fpgc.sdramcontroller.SDRAM_WEn
-@200
--
--SPI flash
-@28
-FPGC_tb.spiFlash.CLK
-FPGC_tb.spiFlash.CSn
-FPGC_tb.spiFlash.DIO
-FPGC_tb.spiFlash.DO
-FPGC_tb.spiFlash.HOLDn
-FPGC_tb.spiFlash.WPn
-@200
--
--
--MU
-@22
-FPGC_tb.fpgc.mu.bus_addr[26:0]
-FPGC_tb.fpgc.mu.bus_d_reg[31:0]
-FPGC_tb.fpgc.mu.bus_data[31:0]
-@28
-FPGC_tb.fpgc.mu.bus_done
-FPGC_tb.fpgc.mu.bus_done_next
-@22
-FPGC_tb.fpgc.mu.bus_q[31:0]
-FPGC_tb.fpgc.mu.bus_q_wire[31:0]
-FPGC_tb.fpgc.mu.bus_q_wire_reg[31:0]
-@28
-FPGC_tb.fpgc.mu.bus_start
-FPGC_tb.fpgc.mu.bus_we
-@200
--
--
 -Fetch
-@28
-FPGC_tb.fpgc.cpu.instr_DE[31:0]
 @24
-FPGC_tb.fpgc.cpu.pc_FE[31:0]
-@28
-FPGC_tb.fpgc.cpu.instr_hit_FE
-@200
--
-@28
-FPGC_tb.fpgc.cpu.intDisabled
-@22
-FPGC_tb.fpgc.cpu.interruptValid
-FPGC_tb.fpgc.cpu.pc_FE[31:0]
-FPGC_tb.fpgc.cpu.pc_FE_backup[31:0]
-FPGC_tb.fpgc.cpu.PC_backup_current[31:0]
+FPGC_tb.fpgc.cpu.pc4_FE[31:0]
 @200
 -
-@28
-FPGC_tb.fpgc.cpu.instr_MEM[31:0]
-FPGC_tb.fpgc.cpu.jumpc_MEM
-FPGC_tb.fpgc.cpu.branch_passed_MEM
+@25
+FPGC_tb.fpgc.cpu.addr_a[31:0]
 @24
-FPGC_tb.fpgc.cpu.jump_addr_MEM[31:0]
-@200
--
-@22
-FPGC_tb.fpgc.mu.bus_addr[26:0]
-@28
-FPGC_tb.fpgc.mu.bus_start
-@22
-FPGC_tb.fpgc.mu.bus_q[31:0]
-FPGC_tb.fpgc.mu.bus_q_wire[31:0]
-@28
-FPGC_tb.fpgc.mu.bus_done_next
-@22
-FPGC_tb.fpgc.mu.bus_q_wire_reg[31:0]
+FPGC_tb.fpgc.cpu.data_a[31:0]
+FPGC_tb.fpgc.cpu.we_a
+FPGC_tb.fpgc.cpu.start_a
 @28
-FPGC_tb.fpgc.mu.bus_done
-@22
-FPGC_tb.fpgc.mu.UART0_rx.o_Rx_Byte[7:0]
-@200
--
-@22
-FPGC_tb.DIPS[3:0]
-@28
-FPGC_tb.fpgc.cpu.intDisabled
-FPGC_tb.fpgc.cpu.interruptValid
-@200
--InstrMem
-@28
-FPGC_tb.fpgc.cpu.instrMem.clk
-@200
--
+FPGC_tb.fpgc.cpu.arbiter_q[31:0]
 @24
-FPGC_tb.fpgc.cpu.instrMem.addr[31:0]
-@22
-FPGC_tb.fpgc.cpu.instrMem.q[31:0]
-@28
-FPGC_tb.fpgc.cpu.instrMem.ignoreNext
-FPGC_tb.fpgc.cpu.instrMem.clear
-FPGC_tb.fpgc.cpu.instrMem.hit
-FPGC_tb.fpgc.cpu.instrMem.hold
+FPGC_tb.fpgc.cpu.done_a
 @200
 -
-@22
-FPGC_tb.fpgc.cpu.instrMem.bus_addr[31:0]
-FPGC_tb.fpgc.cpu.instrMem.bus_data[31:0]
 @28
-FPGC_tb.fpgc.cpu.instrMem.bus_done
-@22
-FPGC_tb.fpgc.cpu.instrMem.bus_q[31:0]
-@28
-FPGC_tb.fpgc.cpu.instrMem.bus_start
-FPGC_tb.fpgc.cpu.instrMem.bus_we
+FPGC_tb.fpgc.cpu.stall_FE
+FPGC_tb.fpgc.cpu.flush_FE
 @200
 -
+-Decode
 -
 @28
-FPGC_tb.fpgc.cpu.clearCache_DE
-FPGC_tb.fpgc.cpu.clearCache_EX
-FPGC_tb.fpgc.cpu.clearCache_MEM
+FPGC_tb.fpgc.cpu.stall_DE
+FPGC_tb.fpgc.cpu.flush_DE
 @200
 -
+-Execute
 -
--
--DataMem
-@22
-FPGC_tb.fpgc.cpu.dataMem.bus_addr[31:0]
-FPGC_tb.fpgc.cpu.dataMem.bus_data[31:0]
-FPGC_tb.fpgc.cpu.dataMem.bus_q[31:0]
-@28
-FPGC_tb.fpgc.cpu.dataMem.bus_we
-FPGC_tb.fpgc.cpu.dataMem.bus_start
-FPGC_tb.fpgc.cpu.dataMem.bus_done
-@200
--
-@24
-FPGC_tb.fpgc.cpu.dataMem.bus_addr[31:0]
 @28
-FPGC_tb.fpgc.cpu.dataMem.busy
-@22
-FPGC_tb.fpgc.cpu.dataMem.qreg[31:0]
-FPGC_tb.fpgc.cpu.dataMem.q[31:0]
+FPGC_tb.fpgc.cpu.stall_EX
+FPGC_tb.fpgc.cpu.flush_EX
 @200
 -
--
--
+-Memory
 -
 @28
-FPGC_tb.fpgc.cpu.clearCache_DE
-FPGC_tb.fpgc.cpu.clearCache_EX
-FPGC_tb.fpgc.cpu.clearCache_MEM
+FPGC_tb.fpgc.cpu.stall_MEM
+FPGC_tb.fpgc.cpu.flush_MEM
 @200
 -
--L2Cache
-@24
-FPGC_tb.fpgc.l2cache.state[2:0]
-FPGC_tb.fpgc.l2cache.clear_cache_counter[15:0]
-@200
+-Write Back
 -
 @28
-FPGC_tb.fpgc.l2cache.start_registered
-@24
-FPGC_tb.fpgc.l2cache.cache_addr[9:0]
-@22
-FPGC_tb.fpgc.l2cache.cache_d[46:0]
-@28
-FPGC_tb.fpgc.l2cache.cache_we
-@22
-FPGC_tb.fpgc.l2cache.cache_q[46:0]
-@200
--
--
--
+FPGC_tb.fpgc.cpu.stall_WB
+FPGC_tb.fpgc.cpu.flush_WB
 [pattern_trace] 1
 [pattern_trace] 0

Verilog/output/FPGC_50.gtkw

@@ -0,0 +1,315 @@
+[*]
+[*] GTKWave Analyzer v3.3.107 (w)1999-2020 BSI
+[*] Sat Sep  2 21:10:16 2023
+[*]
+[dumpfile] "/home/bart/Documents/FPGA/FPGC6/Verilog/output/wave.vcd"
+[dumpfile_mtime] "Sat Sep  2 16:09:11 2023"
+[dumpfile_size] 46133170
+[savefile] "/home/bart/Documents/FPGA/FPGC6/Verilog/output/FPGC.gtkw"
+[timestart] 25540000
+[size] 1920 1054
+[pos] -1 -1
+*-21.666576 1263700 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] FPGC_tb.
+[treeopen] FPGC_tb.fpgc.
+[treeopen] FPGC_tb.fpgc.cpu.arbiter.
+[sst_width] 227
+[signals_width] 366
+[sst_expanded] 1
+[sst_vpaned_height] 494
+@28
+FPGC_tb.fpgc.clk
+@22
+FPGC_tb.fpgc.cpu.PC[26:0]
+@200
+-
+-
+-Arbiter
+-
+@22
+FPGC_tb.fpgc.cpu.arbiter.addr_a[31:0]
+FPGC_tb.fpgc.cpu.arbiter.data_a[31:0]
+@28
+FPGC_tb.fpgc.cpu.arbiter.we_a
+FPGC_tb.fpgc.cpu.arbiter.start_a
+FPGC_tb.fpgc.cpu.arbiter.done_a
+@22
+FPGC_tb.fpgc.cpu.arbiter.q[31:0]
+@200
+-
+-
+@22
+FPGC_tb.fpgc.cpu.arbiter.addr_b[31:0]
+FPGC_tb.fpgc.cpu.arbiter.data_b[31:0]
+@28
+FPGC_tb.fpgc.cpu.arbiter.we_b
+FPGC_tb.fpgc.cpu.arbiter.start_b
+FPGC_tb.fpgc.cpu.arbiter.done_b
+@22
+FPGC_tb.fpgc.cpu.arbiter.q[31:0]
+@200
+-
+-
+@22
+FPGC_tb.fpgc.cpu.arbiter.bus_addr[26:0]
+FPGC_tb.fpgc.cpu.arbiter.bus_data[31:0]
+@28
+FPGC_tb.fpgc.cpu.arbiter.bus_we
+FPGC_tb.fpgc.cpu.arbiter.bus_start
+@29
+FPGC_tb.fpgc.cpu.arbiter.bus_done
+@200
+-
+-
+@24
+FPGC_tb.fpgc.cpu.arbiter.state[2:0]
+@200
+-
+-
+-
+-
+-
+-
+@22
+FPGC_tb.fpgc.cpu.arbiter_bus_addr[26:0]
+FPGC_tb.fpgc.cpu.arbiter_bus_data[31:0]
+@28
+FPGC_tb.fpgc.cpu.arbiter_bus_start
+FPGC_tb.fpgc.cpu.arbiter_bus_we
+@22
+FPGC_tb.fpgc.cpu.arbiter_bus_q[31:0]
+@28
+FPGC_tb.fpgc.cpu.arbiter_bus_done
+@200
+-
+@22
+FPGC_tb.fpgc.cpu.bus_addr[26:0]
+FPGC_tb.fpgc.cpu.bus_data[31:0]
+@28
+FPGC_tb.fpgc.cpu.bus_we
+FPGC_tb.fpgc.cpu.bus_start
+@22
+FPGC_tb.fpgc.cpu.bus_q[31:0]
+@28
+FPGC_tb.fpgc.cpu.bus_done
+@200
+-
+@22
+FPGC_tb.fpgc.cpu.sdc_addr[23:0]
+FPGC_tb.fpgc.cpu.sdc_data[31:0]
+@28
+FPGC_tb.fpgc.cpu.sdc_we
+FPGC_tb.fpgc.cpu.sdc_start
+@22
+FPGC_tb.fpgc.cpu.sdc_q[31:0]
+@28
+FPGC_tb.fpgc.cpu.sdc_done
+@200
+-
+-SDRAMcontroller
+@24
+FPGC_tb.fpgc.sdramcontroller.sdc_addr[23:0]
+@22
+FPGC_tb.fpgc.sdramcontroller.sdc_data[31:0]
+@28
+FPGC_tb.fpgc.sdramcontroller.sdc_we
+FPGC_tb.fpgc.sdramcontroller.sdc_start
+FPGC_tb.fpgc.sdramcontroller.sdc_done
+@24
+FPGC_tb.fpgc.sdramcontroller.state[4:0]
+@28
+FPGC_tb.fpgc.sdramcontroller.is_refreshing
+@22
+FPGC_tb.fpgc.sdramcontroller.sdc_q[31:0]
+@200
+-
+-
+@22
+FPGC_tb.fpgc.sdramcontroller.SDRAM_A[12:0]
+@28
+FPGC_tb.fpgc.sdramcontroller.SDRAM_BA[1:0]
+FPGC_tb.fpgc.sdramcontroller.SDRAM_CASn
+FPGC_tb.fpgc.sdramcontroller.SDRAM_CKE
+@22
+FPGC_tb.fpgc.sdramcontroller.SDRAM_CMD[3:0]
+@28
+FPGC_tb.fpgc.sdramcontroller.SDRAM_CSn
+@22
+FPGC_tb.fpgc.sdramcontroller.SDRAM_DATA[31:0]
+FPGC_tb.fpgc.sdramcontroller.SDRAM_DQM[3:0]
+FPGC_tb.fpgc.sdramcontroller.SDRAM_DQ[31:0]
+@28
+FPGC_tb.fpgc.sdramcontroller.SDRAM_DQ_OE
+@22
+FPGC_tb.fpgc.sdramcontroller.SDRAM_Q[31:0]
+@28
+FPGC_tb.fpgc.sdramcontroller.SDRAM_RASn
+FPGC_tb.fpgc.sdramcontroller.SDRAM_WEn
+@200
+-
+-SPI flash
+@28
+FPGC_tb.spiFlash.CLK
+FPGC_tb.spiFlash.CSn
+FPGC_tb.spiFlash.DIO
+FPGC_tb.spiFlash.DO
+FPGC_tb.spiFlash.HOLDn
+FPGC_tb.spiFlash.WPn
+@200
+-
+-
+-MU
+@22
+FPGC_tb.fpgc.mu.bus_addr[26:0]
+FPGC_tb.fpgc.mu.bus_d_reg[31:0]
+FPGC_tb.fpgc.mu.bus_data[31:0]
+@28
+FPGC_tb.fpgc.mu.bus_done
+FPGC_tb.fpgc.mu.bus_done_next
+@22
+FPGC_tb.fpgc.mu.bus_q[31:0]
+FPGC_tb.fpgc.mu.bus_q_wire[31:0]
+FPGC_tb.fpgc.mu.bus_q_wire_reg[31:0]
+@28
+FPGC_tb.fpgc.mu.bus_start
+FPGC_tb.fpgc.mu.bus_we
+@200
+-
+-
+-Fetch
+@28
+FPGC_tb.fpgc.cpu.instr_DE[31:0]
+@24
+FPGC_tb.fpgc.cpu.pc_FE[31:0]
+@28
+FPGC_tb.fpgc.cpu.instr_hit_FE
+@200
+-
+@28
+FPGC_tb.fpgc.cpu.intDisabled
+@22
+FPGC_tb.fpgc.cpu.interruptValid
+FPGC_tb.fpgc.cpu.pc_FE[31:0]
+FPGC_tb.fpgc.cpu.pc_FE_backup[31:0]
+FPGC_tb.fpgc.cpu.PC_backup_current[31:0]
+@200
+-
+@28
+FPGC_tb.fpgc.cpu.instr_MEM[31:0]
+FPGC_tb.fpgc.cpu.jumpc_MEM
+FPGC_tb.fpgc.cpu.branch_passed_MEM
+@24
+FPGC_tb.fpgc.cpu.jump_addr_MEM[31:0]
+@200
+-
+@22
+FPGC_tb.fpgc.mu.bus_addr[26:0]
+@28
+FPGC_tb.fpgc.mu.bus_start
+@22
+FPGC_tb.fpgc.mu.bus_q[31:0]
+FPGC_tb.fpgc.mu.bus_q_wire[31:0]
+@28
+FPGC_tb.fpgc.mu.bus_done_next
+@22
+FPGC_tb.fpgc.mu.bus_q_wire_reg[31:0]
+@28
+FPGC_tb.fpgc.mu.bus_done
+@22
+FPGC_tb.fpgc.mu.UART0_rx.o_Rx_Byte[7:0]
+@200
+-
+@22
+FPGC_tb.DIPS[3:0]
+@28
+FPGC_tb.fpgc.cpu.intDisabled
+FPGC_tb.fpgc.cpu.interruptValid
+@200
+-InstrMem
+@28
+FPGC_tb.fpgc.cpu.instrMem.clk
+@200
+-
+@24
+FPGC_tb.fpgc.cpu.instrMem.addr[31:0]
+@22
+FPGC_tb.fpgc.cpu.instrMem.q[31:0]
+@28
+FPGC_tb.fpgc.cpu.instrMem.ignoreNext
+FPGC_tb.fpgc.cpu.instrMem.clear
+FPGC_tb.fpgc.cpu.instrMem.hit
+FPGC_tb.fpgc.cpu.instrMem.hold
+@200
+-
+@22
+FPGC_tb.fpgc.cpu.instrMem.bus_addr[31:0]
+FPGC_tb.fpgc.cpu.instrMem.bus_data[31:0]
+@28
+FPGC_tb.fpgc.cpu.instrMem.bus_done
+@22
+FPGC_tb.fpgc.cpu.instrMem.bus_q[31:0]
+@28
+FPGC_tb.fpgc.cpu.instrMem.bus_start
+FPGC_tb.fpgc.cpu.instrMem.bus_we
+@200
+-
+-
+@28
+FPGC_tb.fpgc.cpu.clearCache_DE
+FPGC_tb.fpgc.cpu.clearCache_EX
+FPGC_tb.fpgc.cpu.clearCache_MEM
+@200
+-
+-
+-
+-DataMem
+@22
+FPGC_tb.fpgc.cpu.dataMem.bus_addr[31:0]
+FPGC_tb.fpgc.cpu.dataMem.bus_data[31:0]
+FPGC_tb.fpgc.cpu.dataMem.bus_q[31:0]
+@28
+FPGC_tb.fpgc.cpu.dataMem.bus_we
+FPGC_tb.fpgc.cpu.dataMem.bus_start
+FPGC_tb.fpgc.cpu.dataMem.bus_done
+@200
+-
+@24
+FPGC_tb.fpgc.cpu.dataMem.bus_addr[31:0]
+@28
+FPGC_tb.fpgc.cpu.dataMem.busy
+@22
+FPGC_tb.fpgc.cpu.dataMem.qreg[31:0]
+FPGC_tb.fpgc.cpu.dataMem.q[31:0]
+@200
+-
+-
+-
+-
+@28
+FPGC_tb.fpgc.cpu.clearCache_DE
+FPGC_tb.fpgc.cpu.clearCache_EX
+FPGC_tb.fpgc.cpu.clearCache_MEM
+@200
+-
+-L2Cache
+@24
+FPGC_tb.fpgc.l2cache.state[2:0]
+FPGC_tb.fpgc.l2cache.clear_cache_counter[15:0]
+@200
+-
+@28
+FPGC_tb.fpgc.l2cache.start_registered
+@24
+FPGC_tb.fpgc.l2cache.cache_addr[9:0]
+@22
+FPGC_tb.fpgc.l2cache.cache_d[46:0]
+@28
+FPGC_tb.fpgc.l2cache.cache_we
+@22
+FPGC_tb.fpgc.l2cache.cache_q[46:0]
+@200
+-
+-
+-
+[pattern_trace] 1
+[pattern_trace] 0

Verilog/testbench/FPGC_100MHz_tb.v

@@ -0,0 +1,90 @@
+/*
+ * Testbench
+ * Simulates the entire FPGC
+ * 100MHz experiment
+*/
+
+// Set timescale
+`timescale 1 ns/1 ns
+
+// tld
+`include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/FPGC6.v"
+
+// other logic
+`include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/MultiStabilizer.v"
+
+// cpu
+`include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/CPU.v"
+`include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/ALU.v"
+`include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/ControlUnit.v"
+`include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/InstructionDecoder.v"
+`include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/Regbank.v"
+`include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/Stack.v"
+`include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/InstrMem.v"
+`include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/DataMem.v"
+`include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/Regr.v"
+`include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/Arbiter.v"
+`include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/IntController.v"
+
+// memory
+`include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/SRAM.v"
+`include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/L1Dcache.v"
+`include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/MemoryUnit.v"
+
+
+// Define testmodule
+module FPGC_tb;
+
+//Clock I/O
+reg clk;
+reg nreset;
+
+//Led I/O
+wire led;
+
+FPGC6 fpgc (
+.clk(clk),
+.nreset(nreset),
+     
+//Led for debugging
+.led(led)
+);
+
+
+
+initial
+begin
+    //Dump everything for GTKwave
+    $dumpfile("/home/bart/Documents/FPGA/FPGC6/Verilog/output/wave.vcd");
+    $dumpvars;
+    
+    clk = 0;
+    nreset = 1;
+
+
+    repeat(3)
+    begin
+        #5 clk = ~clk; //100MHz
+        #5 clk = ~clk;
+    end
+
+    nreset = 0;
+
+    repeat(3)
+    begin
+        #5 clk = ~clk; //100MHz
+        #5 clk = ~clk;
+    end
+
+    nreset = 1;
+
+    repeat(1000)
+    begin
+        #5 clk = ~clk; //100MHz
+        #5 clk = ~clk;
+    end
+
+    #1 $finish;
+end
+
+endmodule