Reverted L2 cache size to 1024 words for easier debugging.

Quartus/modules/Memory/L2cache.v

@@ -28,29 +28,27 @@ module L2cache(
 wire cache_reset;
 assign cache_reset = 1'b0;
 
-parameter cache_size = 32768;               // cache size in words. 8129*4bytes = 32KiB
-parameter index_size = 15;                  // index size: log2(cache_size)
-parameter tag_size = 9;                     // mem_addr_bits-index_size = 24-13 = 11
+parameter cache_size = 1024;                // cache size in words. 8129*4bytes = 32KiB
+parameter index_size = 10;                  // index size: log2(cache_size)
+parameter tag_size = 14;                    // mem_add_bits-index_size = 24-13 = 11
 parameter cache_line_size = tag_size+32+1;  // tag + word + valid bit
 
 reg [cache_line_size-1:0] cache [0:cache_size-1];   // cache memory
 
-/*
 integer i;
 // init cache to all zeros
 initial
 begin
     for (i = 0; i < cache_size; i = i + 1)
     begin
-        cache[i] = 42'd0;
+        cache[i] = 47'd0;
     end
 end
-*/
 
-reg [index_size-1:0]        cache_addr = 15'd0;
-reg [cache_line_size-1:0]   cache_d = 42'd0;
+reg [index_size-1:0]        cache_addr = 10'd0;
+reg [cache_line_size-1:0]   cache_d = 47'd0;
 reg                         cache_we = 1'b0;
-reg [cache_line_size-1:0]   cache_q = 42'd0;
+reg [cache_line_size-1:0]   cache_q = 47'd0;
 always @(posedge clk) 
 begin
     cache_q <= cache[cache_addr];
@@ -141,7 +139,7 @@ begin
                 begin
                     clear_cache_counter <= clear_cache_counter + 1'b1;
                     cache_we <= 1'b1;
-                    cache_d <= 42'd0;
+                    cache_d <= 47'd0;
                     cache_addr <= clear_cache_counter;
                 end
                 
@@ -190,7 +188,7 @@ begin
             begin
                 if (sdc_done)
                 begin
-                    state <= state_done_high;
+                    state <= state_idle;
 
                     sdc_addr_reg <= 24'd0;
                     sdc_we_reg <= 1'b0;
@@ -206,9 +204,9 @@ begin
             state_check_cache: 
             begin
                 // check cache. if hit, return cached item
-                if (cache_q[41] && sdc_addr_reg[23:index_size] == cache_q[40:32]) // valid and tag check
+                if (cache_q[46] && sdc_addr_reg[23:index_size] == cache_q[45:32]) // valid and tag check
                 begin
-                    state <= state_done_high;
+                    state <= state_idle;
 
                     l2_done_reg <= 1'b1;
                     l2_q_reg <= cache_q[31:0];
@@ -226,7 +224,7 @@ begin
             begin
                 if (sdc_done)
                 begin
-                    state <= state_done_high;
+                    state <= state_idle;
 
                     // we received item from ram, now write to cache and return
                     sdc_addr_reg <= 24'd0;

Verilog/modules/Memory/L2cache.v

@@ -28,9 +28,9 @@ module L2cache(
 wire cache_reset;
 assign cache_reset = 1'b0;
 
-parameter cache_size = 32768;               // cache size in words. 8129*4bytes = 32KiB
-parameter index_size = 15;                  // index size: log2(cache_size)
-parameter tag_size = 9;                     // mem_addr_bits-index_size = 24-13 = 11
+parameter cache_size = 1024;                // cache size in words. 8129*4bytes = 32KiB
+parameter index_size = 10;                  // index size: log2(cache_size)
+parameter tag_size = 14;                    // mem_add_bits-index_size = 24-13 = 11
 parameter cache_line_size = tag_size+32+1;  // tag + word + valid bit
 
 reg [cache_line_size-1:0] cache [0:cache_size-1];   // cache memory
@@ -41,14 +41,14 @@ initial
 begin
     for (i = 0; i < cache_size; i = i + 1)
     begin
-        cache[i] = 42'd0;
+        cache[i] = 47'd0;
     end
 end
 
-reg [index_size-1:0]        cache_addr = 15'd0;
-reg [cache_line_size-1:0]   cache_d = 42'd0;
+reg [index_size-1:0]        cache_addr = 10'd0;
+reg [cache_line_size-1:0]   cache_d = 47'd0;
 reg                         cache_we = 1'b0;
-reg [cache_line_size-1:0]   cache_q = 42'd0;
+reg [cache_line_size-1:0]   cache_q = 47'd0;
 always @(posedge clk) 
 begin
     cache_q <= cache[cache_addr];
@@ -139,7 +139,7 @@ begin
                 begin
                     clear_cache_counter <= clear_cache_counter + 1'b1;
                     cache_we <= 1'b1;
-                    cache_d <= 42'd0;
+                    cache_d <= 47'd0;
                     cache_addr <= clear_cache_counter;
                 end
                 
@@ -188,7 +188,7 @@ begin
             begin
                 if (sdc_done)
                 begin
-                    state <= state_done_high;
+                    state <= state_idle;
 
                     sdc_addr_reg <= 24'd0;
                     sdc_we_reg <= 1'b0;
@@ -204,9 +204,9 @@ begin
             state_check_cache: 
             begin
                 // check cache. if hit, return cached item
-                if (cache_q[41] && sdc_addr_reg[23:index_size] == cache_q[40:32]) // valid and tag check
+                if (cache_q[46] && sdc_addr_reg[23:index_size] == cache_q[45:32]) // valid and tag check
                 begin
-                    state <= state_done_high;
+                    state <= state_idle;
 
                     l2_done_reg <= 1'b1;
                     l2_q_reg <= cache_q[31:0];
@@ -224,7 +224,7 @@ begin
             begin
                 if (sdc_done)
                 begin
-                    state <= state_done_high;
+                    state <= state_idle;
 
                     // we received item from ram, now write to cache and return
                     sdc_addr_reg <= 24'd0;