Changed pixelplane to 24 bit colors. Updated texture generator and raycaster to 24 bit color.

Graphics/Raycast/generateTextures.py

@@ -9,10 +9,6 @@ from PIL import Image
 
 TEXTURE_NAME = "colorstone"
 
-rmap = [0,36,72,109,145,182,218,255]
-gmap = [0,36,72,109,145,182,218,255]
-bmap = [0,85,170,255]
-
 # print(str(doubleToFP16(planeY)) + ", ", end='')
 
 im = Image.open("Textures/" + TEXTURE_NAME + ".png")
@@ -24,10 +20,7 @@ for x in range(tex_array.shape[0]):
         r = tex_array[x][y][0]
         g = tex_array[x][y][1]
         b = tex_array[x][y][2]
-        rval = min(range(len(rmap)), key=lambda i: abs(rmap[i]-r))
-        gval = min(range(len(gmap)), key=lambda i: abs(gmap[i]-g))
-        bval = min(range(len(bmap)), key=lambda i: abs(bmap[i]-b))
-        print(str(rval*32+gval*4+bval) + ", ", end='')
+        print(str(r*2**16+g*2**8+b) + ", ", end='')
     print()
 
 print("},")

Quartus/modules/FPGC.v

@@ -395,22 +395,22 @@ VRAM #(
 //VRAMPX I/O
 wire        vramPX_gpu_clk;
 wire [16:0] vramPX_gpu_addr;
-wire [7:0]  vramPX_gpu_d;
+wire [23:0]  vramPX_gpu_d;
 wire        vramPX_gpu_we;
-wire [7:0]  vramPX_gpu_q;
+wire [23:0]  vramPX_gpu_q;
 
 wire        vramPX_cpu_clk;
 wire [16:0] vramPX_cpu_addr;
-wire [7:0]  vramPX_cpu_d;
+wire [23:0]  vramPX_cpu_d;
 wire        vramPX_cpu_we;
-wire [7:0]  vramPX_cpu_q;
+wire [23:0]  vramPX_cpu_q;
 
 // FSX will not write to VRAM
 assign vramPX_gpu_we     = 1'b0;
-assign vramPX_gpu_d      = 8'd0;
+assign vramPX_gpu_d      = 24'd0;
 
 VRAM #(
-.WIDTH(8),
+.WIDTH(24),
 .WORDS(76800),
 .ADDR_BITS(17),
 .LIST("memory/vramPX.list")

Quartus/modules/GPU/FSX.v

@@ -38,7 +38,7 @@ module FSX(
 
     //VRAMpixel
     output [16:0]       vramPX_addr,
-    input  [7:0]        vramPX_q,
+    input  [23:0]       vramPX_q,
 
     //Interrupt signal
     output              frameDrawn
@@ -159,9 +159,9 @@ BGWrenderer bgwrenderer(
 );
 
 
-wire [2:0] PX_r;
-wire [2:0] PX_g;
-wire [1:0] PX_b;
+wire [7:0] PX_r;
+wire [7:0] PX_g;
+wire [7:0] PX_b;
 
 
 PixelEngine pixelEngine(
@@ -186,44 +186,25 @@ PixelEngine pixelEngine(
     .vram_q(vramPX_q)
 );
 
+
 // Give priority to pixel plane if bgw plane is black
 wire pxPriority = (BGW_r == 3'd0 && BGW_g == 3'd0 && BGW_b == 2'd0);
 
-wire [2:0] rendered_r;
-wire [2:0] rendered_g;
-wire [1:0] rendered_b;
-
-assign rendered_r = (pxPriority) ? PX_r: BGW_r;
-assign rendered_g = (pxPriority) ? PX_g: BGW_g;
-assign rendered_b = (pxPriority) ? PX_b : BGW_b;
-
-/*
-assign r_ntsc = (!selectOutput) ? rendered_r : 3'd0;
-assign g_ntsc = (!selectOutput) ? rendered_g : 3'd0;
-assign b_ntsc = (!selectOutput) ? rendered_b : 2'd0;
-*/
-
-wire [2:0] r_hdmi;
-wire [2:0] g_hdmi;
-wire [1:0] b_hdmi;
-
-/*
-assign r_hdmi = (selectOutput) ? rendered_r : 3'd0;
-assign g_hdmi = (selectOutput) ? rendered_g : 3'd0;
-assign b_hdmi = (selectOutput) ? rendered_b : 2'd0;
-*/
+wire [7:0] BGW_r_Byte;
+wire [7:0] BGW_g_Byte;
+wire [7:0] BGW_b_Byte;
 
-assign r_hdmi = rendered_r;
-assign g_hdmi = rendered_g;
-assign b_hdmi = rendered_b;
+assign BGW_r_Byte = (BGW_r == 3'd0) ?  {BGW_r, 5'b00000} : {BGW_r, 5'b11111};
+assign BGW_g_Byte = (BGW_g == 3'd0) ?  {BGW_g, 5'b00000} : {BGW_g, 5'b11111};
+assign BGW_b_Byte = (BGW_b == 2'd0) ?  {BGW_b, 6'b000000} : {BGW_b, 6'b111111};
 
 wire [7:0] rByte;
 wire [7:0] gByte;
 wire [7:0] bByte;
 
-assign rByte = (r_hdmi == 3'd0) ?  {r_hdmi, 5'b00000} : {r_hdmi, 5'b11111};
-assign gByte = (g_hdmi == 3'd0) ?  {g_hdmi, 5'b00000} : {g_hdmi, 5'b11111};
-assign bByte = (b_hdmi == 2'd0) ?  {b_hdmi, 6'b000000} : {b_hdmi, 6'b111111};
+assign rByte = (pxPriority) ? PX_r: BGW_r_Byte;
+assign gByte = (pxPriority) ? PX_g: BGW_g_Byte;
+assign bByte = (pxPriority) ? PX_b : BGW_b_Byte;
 
 
 // Convert VGA signal to HDMI signals

Quartus/modules/GPU/PixelEngine.v

@@ -11,16 +11,16 @@ module PixelEngine(
                                     // note: horizontally this scaling is always applied
 
     // Output pixels
-    output wire [2:0]   r,
-    output wire [2:0]   g,
-    output wire [1:0]   b,
+    output wire [7:0]   r,
+    output wire [7:0]   g,
+    output wire [7:0]   b,
 
     input [11:0]        h_count,  // line position in pixels including blanking 
     input [11:0]        v_count,  // frame position in lines including blanking 
 
     // VRAMpixel
     output wire [16:0] vram_addr,
-    input [7:0]    vram_q
+    input [23:0]    vram_q
 );
 
 localparam HSTART_HDMI = 159; // Pixel to start rendering
@@ -32,8 +32,6 @@ localparam VSTART_NTSC = 19; // Line to start rendering
 wire [9:0] h_start = (scale2x) ? HSTART_HDMI : HSTART_NTSC;
 wire [9:0] v_start = (scale2x) ? VSTART_HDMI : VSTART_NTSC;
 
-reg [7:0] pixel_data = 8'd0;
-
 wire h_active = (h_count > h_start);
 wire v_active = (v_count > v_start);
 
@@ -44,8 +42,8 @@ wire [16:0] pixel_idx = ( (line_active >> scale2x) *320) + (pixel_active >> 1);
 
 assign vram_addr = pixel_idx;
 
-assign r = (blank) ? 3'd0 : vram_q[7:5];
-assign g = (blank) ? 3'd0 : vram_q[4:2];
-assign b = (blank) ? 2'd0 : vram_q[1:0];
+assign r = (blank) ? 8'd0 : vram_q[23:16];
+assign g = (blank) ? 8'd0 : vram_q[15:8];
+assign b = (blank) ? 8'd0 : vram_q[7:0];
 
 endmodule

Quartus/modules/Memory/MemoryUnit.v

@@ -42,10 +42,10 @@ module MemoryUnit(
     input  [8:0]    VRAMspr_cpu_q,
 
     //VRAMpx cpu port
-    output [7:0]    VRAMpx_cpu_d,
+    output [23:0]   VRAMpx_cpu_d,
     output [16:0]   VRAMpx_cpu_addr,
     output          VRAMpx_cpu_we,
-    input  [7:0]    VRAMpx_cpu_q,
+    input  [23:0]   VRAMpx_cpu_q,
 
     //ROM
     output [8:0]    ROM_addr,

Verilog/modules/FPGC6.v

@@ -340,22 +340,22 @@ VRAM #(
 //VRAMPX I/O
 wire        vramPX_gpu_clk;
 wire [16:0] vramPX_gpu_addr;
-wire [7:0]  vramPX_gpu_d;
+wire [23:0]  vramPX_gpu_d;
 wire        vramPX_gpu_we;
-wire [7:0]  vramPX_gpu_q;
+wire [23:0]  vramPX_gpu_q;
 
 wire        vramPX_cpu_clk;
 wire [16:0] vramPX_cpu_addr;
-wire [7:0]  vramPX_cpu_d;
+wire [23:0]  vramPX_cpu_d;
 wire        vramPX_cpu_we;
-wire [7:0]  vramPX_cpu_q;
+wire [23:0]  vramPX_cpu_q;
 
 // FSX will not write to VRAM
 assign vramPX_gpu_we     = 1'b0;
-assign vramPX_gpu_d      = 8'd0;
+assign vramPX_gpu_d      = 24'd0;
 
 VRAM #(
-.WIDTH(8),
+.WIDTH(24),
 .WORDS(76800),
 .ADDR_BITS(17),
 .LIST("memory/vramPX.list")

Verilog/modules/GPU/FSX.v

@@ -38,7 +38,7 @@ module FSX(
 
     //VRAMpixel
     output [16:0]       vramPX_addr,
-    input  [7:0]        vramPX_q,
+    input  [23:0]       vramPX_q,
 
     //Interrupt signal
     output              frameDrawn
@@ -170,9 +170,9 @@ BGWrenderer bgwrenderer(
 );
 
 
-wire [2:0] PX_r;
-wire [2:0] PX_g;
-wire [1:0] PX_b;
+wire [7:0] PX_r;
+wire [7:0] PX_g;
+wire [7:0] PX_b;
 
 
 PixelEngine pixelEngine(
@@ -201,41 +201,21 @@ PixelEngine pixelEngine(
 // Give priority to pixel plane if bgw plane is black
 wire pxPriority = (BGW_r == 3'd0 && BGW_g == 3'd0 && BGW_b == 2'd0);
 
-wire [2:0] rendered_r;
-wire [2:0] rendered_g;
-wire [1:0] rendered_b;
+wire [7:0] BGW_r_Byte;
+wire [7:0] BGW_g_Byte;
+wire [7:0] BGW_b_Byte;
 
-assign rendered_r = (pxPriority) ? PX_r: BGW_r;
-assign rendered_g = (pxPriority) ? PX_g: BGW_g;
-assign rendered_b = (pxPriority) ? PX_b : BGW_b;
-
-/*
-assign r_ntsc = (!selectOutput) ? rendered_r : 3'd0;
-assign g_ntsc = (!selectOutput) ? rendered_g : 3'd0;
-assign b_ntsc = (!selectOutput) ? rendered_b : 2'd0;
-*/
-
-wire [2:0] r_hdmi;
-wire [2:0] g_hdmi;
-wire [1:0] b_hdmi;
-
-/*
-assign r_hdmi = (selectOutput) ? rendered_r : 3'd0;
-assign g_hdmi = (selectOutput) ? rendered_g : 3'd0;
-assign b_hdmi = (selectOutput) ? rendered_b : 2'd0;
-*/
-
-assign r_hdmi = rendered_r;
-assign g_hdmi = rendered_g;
-assign b_hdmi = rendered_b;
+assign BGW_r_Byte = (BGW_r == 3'd0) ?  {BGW_r, 5'b00000} : {BGW_r, 5'b11111};
+assign BGW_g_Byte = (BGW_g == 3'd0) ?  {BGW_g, 5'b00000} : {BGW_g, 5'b11111};
+assign BGW_b_Byte = (BGW_b == 2'd0) ?  {BGW_b, 6'b000000} : {BGW_b, 6'b111111};
 
 wire [7:0] rByte;
 wire [7:0] gByte;
 wire [7:0] bByte;
 
-assign rByte = (r_hdmi == 3'd0) ?  {r_hdmi, 5'b00000} : {r_hdmi, 5'b11111};
-assign gByte = (g_hdmi == 3'd0) ?  {g_hdmi, 5'b00000} : {g_hdmi, 5'b11111};
-assign bByte = (b_hdmi == 2'd0) ?  {b_hdmi, 6'b000000} : {b_hdmi, 6'b111111};
+assign rByte = (pxPriority) ? PX_r: BGW_r_Byte;
+assign gByte = (pxPriority) ? PX_g: BGW_g_Byte;
+assign bByte = (pxPriority) ? PX_b : BGW_b_Byte;
 
 
 // Convert VGA signal to HDMI signals

Verilog/modules/GPU/PixelEngine.v

@@ -11,16 +11,16 @@ module PixelEngine(
                                     // note: horizontally this scaling is always applied
 
     // Output pixels
-    output wire [2:0]   r,
-    output wire [2:0]   g,
-    output wire [1:0]   b,
+    output wire [7:0]   r,
+    output wire [7:0]   g,
+    output wire [7:0]   b,
 
     input [11:0]        h_count,  // line position in pixels including blanking 
     input [11:0]        v_count,  // frame position in lines including blanking 
 
     // VRAMpixel
     output wire [16:0] vram_addr,
-    input [7:0]    vram_q
+    input [23:0]    vram_q
 );
 
 localparam HSTART_HDMI = 159; // Pixel to start rendering
@@ -32,8 +32,6 @@ localparam VSTART_NTSC = 19; // Line to start rendering
 wire [9:0] h_start = (scale2x) ? HSTART_HDMI : HSTART_NTSC;
 wire [9:0] v_start = (scale2x) ? VSTART_HDMI : VSTART_NTSC;
 
-reg [7:0] pixel_data = 8'd0;
-
 wire h_active = (h_count > h_start);
 wire v_active = (v_count > v_start);
 
@@ -44,8 +42,8 @@ wire [16:0] pixel_idx = ( (line_active >> scale2x) *320) + (pixel_active >> 1);
 
 assign vram_addr = pixel_idx;
 
-assign r = (blank) ? 3'd0 : vram_q[7:5];
-assign g = (blank) ? 3'd0 : vram_q[4:2];
-assign b = (blank) ? 2'd0 : vram_q[1:0];
+assign r = (blank) ? 8'd0 : vram_q[23:16];
+assign g = (blank) ? 8'd0 : vram_q[15:8];
+assign b = (blank) ? 8'd0 : vram_q[7:0];
 
 endmodule

Verilog/modules/Memory/MemoryUnit.v

@@ -42,10 +42,10 @@ module MemoryUnit(
     input  [8:0]    VRAMspr_cpu_q,
 
     //VRAMpx cpu port
-    output [7:0]    VRAMpx_cpu_d,
+    output [23:0]   VRAMpx_cpu_d,
     output [16:0]   VRAMpx_cpu_addr,
     output          VRAMpx_cpu_we,
-    input  [7:0]    VRAMpx_cpu_q,
+    input  [23:0]   VRAMpx_cpu_q,
 
     //ROM
     output [8:0]    ROM_addr,