More tests for 100mhz

Quartus/FPGC.qsf

@@ -42,10 +42,10 @@ set_global_assignment -name DEVICE 5CEFA5F23I7
 set_global_assignment -name TOP_LEVEL_ENTITY FPGC
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:46:59  DECEMBER 09, 2022"
-set_global_assignment -name LAST_QUARTUS_VERSION "21.1.1 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "23.1std.0 Lite Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
 set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
@@ -223,12 +223,14 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to GPI[0]
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to GPI[1]
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to GPI[2]
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to GPI[3]
-set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
+set_global_assignment -name OPTIMIZATION_MODE BALANCED
 set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
 set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
 set_global_assignment -name ALM_REGISTER_PACKING_EFFORT LOW
 set_global_assignment -name SDC_FILE FPGC.sdc
 set_global_assignment -name VERILOG_FILE modules/FPGC.v
+set_global_assignment -name QIP_FILE lpmmults.qip
+set_global_assignment -name QIP_FILE lpmmult.qip
 set_global_assignment -name VERILOG_FILE modules/IO/MillisCounter.v
 set_global_assignment -name VERILOG_FILE modules/IO/IDivider.v
 set_global_assignment -name VERILOG_FILE modules/IO/FPDivider.v

Quartus/ddr.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
-set_global_assignment -name IP_TOOL_VERSION "21.1"
+set_global_assignment -name IP_TOOL_VERSION "23.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ddr.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddr_bb.v"]

Quartus/ddr.v

@@ -9,16 +9,16 @@
 // 			ALTDDIO_OUT
 //
 // Simulation Library Files(s):
-// 			altera_mf
+// 			
 // ============================================================
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 21.1.1 Build 850 06/23/2022 SJ Lite Edition
+// 23.1std.0 Build 991 11/28/2023 SC Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2022  Intel Corporation. All rights reserved.
+//Copyright (C) 2023  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
 //and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 
@@ -105,4 +105,3 @@ endmodule
 // Retrieval info: GEN_FILE: TYPE_NORMAL ddr.inc FALSE TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL ddr.cmp FALSE TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL ddr.ppf TRUE FALSE
-// Retrieval info: LIB_FILE: altera_mf

Quartus/ddr_bb.v

@@ -9,15 +9,15 @@
 // 			ALTDDIO_OUT
 //
 // Simulation Library Files(s):
-// 			altera_mf
+// 			
 // ============================================================
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 21.1.1 Build 850 06/23/2022 SJ Lite Edition
+// 23.1std.0 Build 991 11/28/2023 SC Lite Edition
 // ************************************************************
 
-//Copyright (C) 2022  Intel Corporation. All rights reserved.
+//Copyright (C) 2023  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
 //and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 
@@ -74,4 +74,3 @@ endmodule
 // Retrieval info: GEN_FILE: TYPE_NORMAL ddr.inc FALSE TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL ddr.cmp FALSE TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL ddr.ppf TRUE FALSE
-// Retrieval info: LIB_FILE: altera_mf

Quartus/lpmmult.qip

@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
+set_global_assignment -name IP_TOOL_VERSION "23.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpmmult.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpmmult_bb.v"]

Quartus/lpmmult.v

@@ -0,0 +1,111 @@
+// megafunction wizard: %LPM_MULT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_mult 
+
+// ============================================================
+// File Name: lpmmult.v
+// Megafunction Name(s):
+// 			lpm_mult
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 23.1std.0 Build 991 11/28/2023 SC Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2023  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module lpmmult (
+	dataa,
+	datab,
+	result);
+
+	input	[31:0]  dataa;
+	input	[31:0]  datab;
+	output	[31:0]  result;
+
+	wire [31:0] sub_wire0;
+	wire [31:0] result = sub_wire0[31:0];
+
+	lpm_mult	lpm_mult_component (
+				.dataa (dataa),
+				.datab (datab),
+				.result (sub_wire0),
+				.aclr (1'b0),
+				.clken (1'b1),
+				.clock (1'b0),
+				.sclr (1'b0),
+				.sum (1'b0));
+	defparam
+		lpm_mult_component.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=5",
+		lpm_mult_component.lpm_representation = "UNSIGNED",
+		lpm_mult_component.lpm_type = "LPM_MULT",
+		lpm_mult_component.lpm_widtha = 32,
+		lpm_mult_component.lpm_widthb = 32,
+		lpm_mult_component.lpm_widthp = 32;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "0"
+// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
+// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
+// Retrieval info: PRIVATE: Latency NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
+// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
+// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
+// Retrieval info: PRIVATE: WidthA NUMERIC "32"
+// Retrieval info: PRIVATE: WidthB NUMERIC "32"
+// Retrieval info: PRIVATE: WidthP NUMERIC "32"
+// Retrieval info: PRIVATE: aclr NUMERIC "0"
+// Retrieval info: PRIVATE: clken NUMERIC "0"
+// Retrieval info: PRIVATE: new_diagram STRING "1"
+// Retrieval info: PRIVATE: optimize NUMERIC "0"
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+// Retrieval info: CONSTANT: LPM_HINT STRING "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=5"
+// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
+// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "32"
+// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "32"
+// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "32"
+// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
+// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
+// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
+// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
+// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
+// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpmmult.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpmmult.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpmmult.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpmmult.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpmmult_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpmmult_bb.v TRUE
+// Retrieval info: LIB_FILE: lpm

Quartus/lpmmult_bb.v

@@ -0,0 +1,85 @@
+// megafunction wizard: %LPM_MULT%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_mult 
+
+// ============================================================
+// File Name: lpmmult.v
+// Megafunction Name(s):
+// 			lpm_mult
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 23.1std.0 Build 991 11/28/2023 SC Lite Edition
+// ************************************************************
+
+//Copyright (C) 2023  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+module lpmmult (
+	dataa,
+	datab,
+	result);
+
+	input	[31:0]  dataa;
+	input	[31:0]  datab;
+	output	[31:0]  result;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "0"
+// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
+// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
+// Retrieval info: PRIVATE: Latency NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
+// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
+// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
+// Retrieval info: PRIVATE: WidthA NUMERIC "32"
+// Retrieval info: PRIVATE: WidthB NUMERIC "32"
+// Retrieval info: PRIVATE: WidthP NUMERIC "32"
+// Retrieval info: PRIVATE: aclr NUMERIC "0"
+// Retrieval info: PRIVATE: clken NUMERIC "0"
+// Retrieval info: PRIVATE: new_diagram STRING "1"
+// Retrieval info: PRIVATE: optimize NUMERIC "0"
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+// Retrieval info: CONSTANT: LPM_HINT STRING "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=5"
+// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
+// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "32"
+// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "32"
+// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "32"
+// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
+// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
+// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
+// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
+// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
+// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpmmult.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpmmult.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpmmult.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpmmult.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpmmult_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpmmult_bb.v TRUE
+// Retrieval info: LIB_FILE: lpm

Quartus/lpmmults.qip

@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
+set_global_assignment -name IP_TOOL_VERSION "23.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpmmults.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpmmults_bb.v"]

Quartus/lpmmults.v

@@ -0,0 +1,111 @@
+// megafunction wizard: %LPM_MULT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_mult 
+
+// ============================================================
+// File Name: lpmmults.v
+// Megafunction Name(s):
+// 			lpm_mult
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 23.1std.0 Build 991 11/28/2023 SC Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2023  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module lpmmults (
+	dataa,
+	datab,
+	result);
+
+	input	[31:0]  dataa;
+	input	[31:0]  datab;
+	output	[63:0]  result;
+
+	wire [63:0] sub_wire0;
+	wire [63:0] result = sub_wire0[63:0];
+
+	lpm_mult	lpm_mult_component (
+				.dataa (dataa),
+				.datab (datab),
+				.result (sub_wire0),
+				.aclr (1'b0),
+				.clken (1'b1),
+				.clock (1'b0),
+				.sclr (1'b0),
+				.sum (1'b0));
+	defparam
+		lpm_mult_component.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=5",
+		lpm_mult_component.lpm_representation = "SIGNED",
+		lpm_mult_component.lpm_type = "LPM_MULT",
+		lpm_mult_component.lpm_widtha = 32,
+		lpm_mult_component.lpm_widthb = 32,
+		lpm_mult_component.lpm_widthp = 64;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
+// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
+// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
+// Retrieval info: PRIVATE: Latency NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
+// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
+// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
+// Retrieval info: PRIVATE: WidthA NUMERIC "32"
+// Retrieval info: PRIVATE: WidthB NUMERIC "32"
+// Retrieval info: PRIVATE: WidthP NUMERIC "64"
+// Retrieval info: PRIVATE: aclr NUMERIC "0"
+// Retrieval info: PRIVATE: clken NUMERIC "0"
+// Retrieval info: PRIVATE: new_diagram STRING "1"
+// Retrieval info: PRIVATE: optimize NUMERIC "0"
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+// Retrieval info: CONSTANT: LPM_HINT STRING "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=5"
+// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
+// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "32"
+// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "32"
+// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "64"
+// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
+// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
+// Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL "result[63..0]"
+// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
+// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
+// Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpmmults.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpmmults.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpmmults.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpmmults.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpmmults_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpmmults_bb.v TRUE
+// Retrieval info: LIB_FILE: lpm

Quartus/lpmmults_bb.v

@@ -0,0 +1,85 @@
+// megafunction wizard: %LPM_MULT%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_mult 
+
+// ============================================================
+// File Name: lpmmults.v
+// Megafunction Name(s):
+// 			lpm_mult
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 23.1std.0 Build 991 11/28/2023 SC Lite Edition
+// ************************************************************
+
+//Copyright (C) 2023  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+module lpmmults (
+	dataa,
+	datab,
+	result);
+
+	input	[31:0]  dataa;
+	input	[31:0]  datab;
+	output	[63:0]  result;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
+// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
+// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
+// Retrieval info: PRIVATE: Latency NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
+// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
+// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
+// Retrieval info: PRIVATE: WidthA NUMERIC "32"
+// Retrieval info: PRIVATE: WidthB NUMERIC "32"
+// Retrieval info: PRIVATE: WidthP NUMERIC "64"
+// Retrieval info: PRIVATE: aclr NUMERIC "0"
+// Retrieval info: PRIVATE: clken NUMERIC "0"
+// Retrieval info: PRIVATE: new_diagram STRING "1"
+// Retrieval info: PRIVATE: optimize NUMERIC "0"
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+// Retrieval info: CONSTANT: LPM_HINT STRING "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=5"
+// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
+// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "32"
+// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "32"
+// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "64"
+// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
+// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
+// Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL "result[63..0]"
+// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
+// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
+// Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpmmults.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpmmults.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpmmults.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpmmults.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpmmults_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpmmults_bb.v TRUE
+// Retrieval info: LIB_FILE: lpm

Quartus/mainpll.bsf

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 2022  Intel Corporation. All rights reserved.
+Copyright (C) 2023  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
 and other software and tools, and any partner logic 
 functions, and any output files from any of the foregoing 

Quartus/mainpll.qip

@@ -1,5 +1,5 @@
 set_global_assignment -entity "mainpll" -library "mainpll" -name IP_TOOL_NAME "altera_pll"
-set_global_assignment -entity "mainpll" -library "mainpll" -name IP_TOOL_VERSION "21.1"
+set_global_assignment -entity "mainpll" -library "mainpll" -name IP_TOOL_VERSION "23.1"
 set_global_assignment -entity "mainpll" -library "mainpll" -name IP_TOOL_ENV "mwpim"
 set_global_assignment -library "mainpll" -name MISC_FILE [file join $::quartus(qip_path) "mainpll.cmp"]
 set_global_assignment -entity "mainpll" -library "mainpll" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
@@ -11,18 +11,19 @@ set_global_assignment -entity "mainpll" -library "mainpll" -name IP_COMPONENT_DI
 set_global_assignment -entity "mainpll" -library "mainpll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
 set_global_assignment -entity "mainpll" -library "mainpll" -name IP_COMPONENT_INTERNAL "Off"
 set_global_assignment -entity "mainpll" -library "mainpll" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
-set_global_assignment -entity "mainpll" -library "mainpll" -name IP_COMPONENT_VERSION "MjEuMQ=="
+set_global_assignment -entity "mainpll" -library "mainpll" -name IP_COMPONENT_VERSION "MjMuMQ=="
 set_global_assignment -entity "mainpll" -library "mainpll" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A="
 set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_NAME "bWFpbnBsbF8wMDAy"
 set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA="
 set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
 set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_INTERNAL "Off"
 set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
-set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_VERSION "MjEuMQ=="
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_VERSION "MjMuMQ=="
 set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A="
 set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
 set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
-set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::VW5rbm93bg==::ZGV2aWNl"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX2RldmljZV9zcGVlZF9ncmFkZQ==::Mg==::RGV2aWNlIFNwZWVkIEdyYWRl"
 set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU="
 set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
 set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
@@ -333,5 +334,5 @@ set_global_assignment -library "mainpll" -name VERILOG_FILE [file join $::quartu
 set_global_assignment -library "mainpll" -name QIP_FILE [file join $::quartus(qip_path) "mainpll/mainpll_0002.qip"]
 
 set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_TOOL_NAME "altera_pll"
-set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_TOOL_VERSION "21.1"
+set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_TOOL_VERSION "23.1"
 set_global_assignment -entity "mainpll_0002" -library "mainpll" -name IP_TOOL_ENV "mwpim"

Quartus/mainpll.sip

@@ -1,5 +1,5 @@
 set_global_assignment -entity "mainpll" -library "lib_mainpll" -name IP_TOOL_NAME "altera_pll"
-set_global_assignment -entity "mainpll" -library "lib_mainpll" -name IP_TOOL_VERSION "21.1"
+set_global_assignment -entity "mainpll" -library "lib_mainpll" -name IP_TOOL_VERSION "23.1"
 set_global_assignment -entity "mainpll" -library "lib_mainpll" -name IP_TOOL_ENV "mwpim"
 set_global_assignment -library "lib_mainpll" -name SPD_FILE [file join $::quartus(sip_path) "mainpll.spd"]
 

Quartus/mainpll.v

@@ -1,8 +1,8 @@
-// megafunction wizard: %PLL Intel FPGA IP v21.1%
+// megafunction wizard: %PLL Intel FPGA IP v23.1%
 // GENERATION: XML
 // mainpll.v
 
-// Generated using ACDS version 21.1 850
+// Generated using ACDS version 23.1 991
 
 `timescale 1 ps / 1 ps
 module mainpll (
@@ -33,7 +33,7 @@ endmodule
 //	************************************************************
 //	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //	************************************************************
-//	Copyright (C) 1991-2023 Altera Corporation
+//	Copyright (C) 1991-2024 Altera Corporation
 //	Any megafunction design, and related net list (encrypted or decrypted),
 //	support information, device programming or simulation file, and any other
 //	associated documentation or information provided by Altera or a partner
@@ -53,12 +53,12 @@ endmodule
 //	their respective licensors.  No other licenses, including any licenses
 //	needed under any third party's intellectual property, are provided herein.
 //-->
-// Retrieval info: <instance entity-name="altera_pll" version="21.1" >
+// Retrieval info: <instance entity-name="altera_pll" version="23.1" >
 // Retrieval info: 	<generic name="debug_print_output" value="false" />
 // Retrieval info: 	<generic name="debug_use_rbc_taf_method" value="false" />
 // Retrieval info: 	<generic name="device_family" value="Cyclone V" />
-// Retrieval info: 	<generic name="device" value="5CEBA2F17A7" />
-// Retrieval info: 	<generic name="gui_device_speed_grade" value="1" />
+// Retrieval info: 	<generic name="device" value="Unknown" />
+// Retrieval info: 	<generic name="gui_device_speed_grade" value="2" />
 // Retrieval info: 	<generic name="gui_pll_mode" value="Integer-N PLL" />
 // Retrieval info: 	<generic name="gui_reference_clock_frequency" value="50.0" />
 // Retrieval info: 	<generic name="gui_channel_spacing" value="0.0" />

Quartus/mainpll/mainpll_0002.v

@@ -37,7 +37,7 @@ module  mainpll_0002(
 		.output_clock_frequency1("100.000000 MHz"),
 		.phase_shift1("5000 ps"),
 		.duty_cycle1(50),
-		.output_clock_frequency2("50.000000 MHz"),
+		.output_clock_frequency2("100.000000 MHz"),
 		.phase_shift2("0 ps"),
 		.duty_cycle2(50),
 		.output_clock_frequency3("25.000000 MHz"),

Quartus/mainpll_sim/aldec/rivierapro_setup.tcl

@@ -1,5 +1,5 @@
 
-# (C) 2001-2023 Altera Corporation. All rights reserved.
+# (C) 2001-2024 Altera Corporation. All rights reserved.
 # Your use of Altera Corporation's design tools, logic functions and 
 # other software and tools, and its AMPP partner logic functions, and 
 # any output files any of the foregoing (including device programming 
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 21.1 850 linux 2023.09.03.15:07:27
+# ACDS 23.1 991 linux 2024.05.19.19:48:27
 # ----------------------------------------
 # Auto-generated simulation script rivierapro_setup.tcl
 # ----------------------------------------
@@ -113,7 +113,7 @@ if ![info exists QSYS_SIMDIR] {
 }
 
 if ![info exists QUARTUS_INSTALL_DIR] { 
-  set QUARTUS_INSTALL_DIR "/home/bart/intelFPGA_lite/21.1/quartus/"
+  set QUARTUS_INSTALL_DIR "/home/bart/intelFPGA_lite/23.1std/quartus/"
 }
 
 if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 

Quartus/mainpll_sim/mainpll.vo

@@ -1,11 +1,11 @@
 //IP Functional Simulation Model
-//VERSION_BEGIN 21.1 cbx_mgl 2022:06:23:22:26:17:SJ cbx_simgen 2022:06:23:22:02:32:SJ  VERSION_END
+//VERSION_BEGIN 23.1 cbx_mgl 2023:11:29:19:43:53:SC cbx_simgen 2023:11:29:19:33:05:SC  VERSION_END
 // synthesis VERILOG_INPUT_VERSION VERILOG_2001
 // altera message_off 10463
 
 
 
-// Copyright (C) 2022  Intel Corporation. All rights reserved.
+// Copyright (C) 2023  Intel Corporation. All rights reserved.
 // Your use of Intel Corporation's design tools, logic functions 
 // and other software and tools, and any partner logic 
 // functions, and any output files from any of the foregoing 

Quartus/mainpll_sim/mentor/msim_setup.tcl

@@ -1,5 +1,5 @@
 
-# (C) 2001-2023 Altera Corporation. All rights reserved.
+# (C) 2001-2024 Altera Corporation. All rights reserved.
 # Your use of Altera Corporation's design tools, logic functions and 
 # other software and tools, and its AMPP partner logic functions, and 
 # any output files any of the foregoing (including device programming 
@@ -94,7 +94,7 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 21.1 850 linux 2023.09.03.15:07:27
+# ACDS 23.1 991 linux 2024.05.19.19:48:27
 
 # ----------------------------------------
 # Initialize variables
@@ -113,7 +113,7 @@ if ![info exists QSYS_SIMDIR] {
 }
 
 if ![info exists QUARTUS_INSTALL_DIR] { 
-  set QUARTUS_INSTALL_DIR "/home/bart/intelFPGA_lite/21.1/quartus/"
+  set QUARTUS_INSTALL_DIR "/home/bart/intelFPGA_lite/23.1std/quartus/"
 }
 
 if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 

Quartus/mainpll_sim/synopsys/vcs/vcs_setup.sh

@@ -1,5 +1,5 @@
 
-# (C) 2001-2023 Altera Corporation. All rights reserved.
+# (C) 2001-2024 Altera Corporation. All rights reserved.
 # Your use of Altera Corporation's design tools, logic functions and 
 # other software and tools, and its AMPP partner logic functions, and 
 # any output files any of the foregoing (including device programming 
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 21.1 850 linux 2023.09.03.15:07:27
+# ACDS 23.1 991 linux 2024.05.19.19:48:27
 
 # ----------------------------------------
 # vcs - auto-generated simulation script
@@ -94,12 +94,12 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 21.1 850 linux 2023.09.03.15:07:27
+# ACDS 23.1 991 linux 2024.05.19.19:48:27
 # ----------------------------------------
 # initialize variables
 TOP_LEVEL_NAME="mainpll"
 QSYS_SIMDIR="./../../"
-QUARTUS_INSTALL_DIR="/home/bart/intelFPGA_lite/21.1/quartus/"
+QUARTUS_INSTALL_DIR="/home/bart/intelFPGA_lite/23.1std/quartus/"
 SKIP_FILE_COPY=0
 SKIP_SIM=0
 USER_DEFINED_ELAB_OPTIONS=""

Quartus/mainpll_sim/synopsys/vcsmx/vcsmx_setup.sh

@@ -1,5 +1,5 @@
 
-# (C) 2001-2023 Altera Corporation. All rights reserved.
+# (C) 2001-2024 Altera Corporation. All rights reserved.
 # Your use of Altera Corporation's design tools, logic functions and 
 # other software and tools, and its AMPP partner logic functions, and 
 # any output files any of the foregoing (including device programming 
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 21.1 850 linux 2023.09.03.15:07:27
+# ACDS 23.1 991 linux 2024.05.19.19:48:27
 
 # ----------------------------------------
 # vcsmx - auto-generated simulation script
@@ -107,12 +107,12 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 21.1 850 linux 2023.09.03.15:07:27
+# ACDS 23.1 991 linux 2024.05.19.19:48:27
 # ----------------------------------------
 # initialize variables
 TOP_LEVEL_NAME="mainpll"
 QSYS_SIMDIR="./../../"
-QUARTUS_INSTALL_DIR="/home/bart/intelFPGA_lite/21.1/quartus/"
+QUARTUS_INSTALL_DIR="/home/bart/intelFPGA_lite/23.1std/quartus/"
 SKIP_FILE_COPY=0
 SKIP_DEV_COM=0
 SKIP_COM=0

Quartus/mainpll_sim/xcelium/cds.lib

@@ -0,0 +1,19 @@
+
+DEFINE std                   $CDS_ROOT/tools/inca/files/STD/           
+DEFINE synopsys              $CDS_ROOT/tools/inca/files/SYNOPSYS/      
+DEFINE ieee                  $CDS_ROOT/tools/inca/files/IEEE/          
+DEFINE ambit                 $CDS_ROOT/tools/inca/files/AMBIT/         
+DEFINE vital_memory          $CDS_ROOT/tools/inca/files/VITAL_MEMORY/  
+DEFINE ncutils               $CDS_ROOT/tools/inca/files/NCUTILS/       
+DEFINE ncinternal            $CDS_ROOT/tools/inca/files/NCINTERNAL/    
+DEFINE ncmodels              $CDS_ROOT/tools/inca/files/NCMODELS/      
+DEFINE cds_assertions        $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
+DEFINE work                  ./libraries/work/                         
+DEFINE altera_ver            ./libraries/altera_ver/                   
+DEFINE lpm_ver               ./libraries/lpm_ver/                      
+DEFINE sgate_ver             ./libraries/sgate_ver/                    
+DEFINE altera_mf_ver         ./libraries/altera_mf_ver/                
+DEFINE altera_lnsim_ver      ./libraries/altera_lnsim_ver/             
+DEFINE cyclonev_ver          ./libraries/cyclonev_ver/                 
+DEFINE cyclonev_hssi_ver     ./libraries/cyclonev_hssi_ver/            
+DEFINE cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver/        

Quartus/mainpll_sim/xcelium/hdl.var

@@ -0,0 +1,2 @@
+
+DEFINE WORK work

Quartus/mainpll_sim/xcelium/xcelium_setup.sh

@@ -0,0 +1,195 @@
+
+# (C) 2001-2024 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 23.1 991 linux 2024.05.19.19:48:27
+
+# ----------------------------------------
+# xcelium - auto-generated simulation script
+
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     mainpll
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# Xcelium Simulation Script.
+# To write a top-level shell script that compiles Intel simulation libraries
+# and the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "xcelium_sim.sh", and modify text as directed.
+# 
+# You can also modify the simulation flow to suit your needs. Set the
+# following variables to 1 to disable their corresponding processes:
+# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
+# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
+# - SKIP_COM: skip compiling Quartus-generated IP simulation files
+# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator. In this case, you must also copy the generated files
+# # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated - 
+# # into the location from which you launch the simulator, or incorporate
+# # into any existing library setup.
+# #
+# # Run Quartus-generated IP simulation script once to compile Quartus EDA
+# # simulation libraries and Quartus-generated IP simulation files, and copy
+# # any ROM/RAM initialization files to the simulation directory.
+# # - If necessary, specify any compilation options:
+# #   USER_DEFINED_COMPILE_OPTIONS
+# #   USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
+# #   USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
+# #
+# source <script generation output directory>/xcelium/xcelium_setup.sh \
+# SKIP_ELAB=1 \
+# SKIP_SIM=1 \
+# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
+# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
+# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
+# QSYS_SIMDIR=<script generation output directory>
+# #
+# # Compile all design files and testbench files, including the top level.
+# # (These are all the files required for simulation other than the files
+# # compiled by the IP script)
+# #
+# xmvlog <compilation options> <design and testbench files>
+# #
+# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
+# # testbench module/entity name.
+# #
+# # Run the IP script again to elaborate and simulate the top level:
+# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
+# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
+# #   until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
+# #
+# source <script generation output directory>/xcelium/xcelium_setup.sh \
+# SKIP_FILE_COPY=1 \
+# SKIP_DEV_COM=1 \
+# SKIP_COM=1 \
+# TOP_LEVEL_NAME=<simulation top> \
+# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
+# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If mainpll is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 23.1 991 linux 2024.05.19.19:48:27
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="mainpll"
+QSYS_SIMDIR="./../"
+QUARTUS_INSTALL_DIR="/home/bart/intelFPGA_lite/23.1std/quartus/"
+SKIP_FILE_COPY=0
+SKIP_DEV_COM=0
+SKIP_COM=0
+SKIP_ELAB=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
+
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for 
+# overwriting variables. An example usage:
+#   sh <simulator>_setup.sh SKIP_SIM=1
+for expression in "$@"; do
+  eval $expression
+  if [ $? -ne 0 ]; then
+    echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+    exit $?
+  fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `xmsim -version` != *"xmsim(64)"* ]]; then
+  :
+else
+  :
+fi
+
+# ----------------------------------------
+# create compilation libraries
+mkdir -p ./libraries/work/
+mkdir -p ./libraries/altera_ver/
+mkdir -p ./libraries/lpm_ver/
+mkdir -p ./libraries/sgate_ver/
+mkdir -p ./libraries/altera_mf_ver/
+mkdir -p ./libraries/altera_lnsim_ver/
+mkdir -p ./libraries/cyclonev_ver/
+mkdir -p ./libraries/cyclonev_hssi_ver/
+mkdir -p ./libraries/cyclonev_pcie_hip_ver/
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+# ----------------------------------------
+# compile device library files
+if [ $SKIP_DEV_COM -eq 0 ]; then
+  xmvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"                      -work altera_ver           
+  xmvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                               -work lpm_ver              
+  xmvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                                  -work sgate_ver            
+  xmvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                              -work altera_mf_ver        
+  xmvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                          -work altera_lnsim_ver     
+  xmvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_atoms_ncrypt.v"          -work cyclonev_ver         
+  xmvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_hmi_atoms_ncrypt.v"      -work cyclonev_ver         
+  xmvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v"                         -work cyclonev_ver         
+  xmvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_hssi_atoms_ncrypt.v"     -work cyclonev_hssi_ver    
+  xmvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v"                    -work cyclonev_hssi_ver    
+  xmvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
+  xmvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v"                -work cyclonev_pcie_hip_ver
+fi
+
+# ----------------------------------------
+# compile design files in correct order
+if [ $SKIP_COM -eq 0 ]; then
+  xmvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/mainpll.vo"
+fi
+
+# ----------------------------------------
+# elaborate top level design
+if [ $SKIP_ELAB -eq 0 ]; then
+  xmelab -update -access +w+r+c -namemap_mixgen +DISABLEGENCHK -relax $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
+fi
+
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+  eval xmsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
+fi

Quartus/modules/CPU/ALU.v

@@ -3,11 +3,14 @@
 */
 
 module ALU(
-    input       [31:0]  a, b,
+	input clk,
+    input       [31:0]  ax, bx,
     input       [3:0]   opcode,
     output reg  [31:0]  y
 );
 
+reg [31:0] a, b;
+
 // Opcodes
 localparam 
     OP_OR       = 4'b0000, // OR
@@ -29,6 +32,21 @@ localparam
 
 reg signed [63:0] ab; // result for FPMULTS
 
+reg [3:0] opcode_reg;
+
+always @(posedge clk)
+begin
+	opcode_reg <= opcode;
+	a <= ax;
+	b <= bx;
+end
+
+wire [31:0] multu_out;
+wire signed [63:0] mults_out;
+
+assign multu_out = a + b;
+assign mults_out = a - b;
+
 always @ (*) 
 begin
     case (opcode)
@@ -40,8 +58,8 @@ begin
         OP_SHIFTL:  y = a << b;
         OP_SHIFTR:  y = a >> b;
         OP_NOTA:    y = ~a;
-        OP_MULTS:   y = $signed(a) * $signed(b);
-        OP_MULTU:   y = a * b;
+        OP_MULTS:   y = mults_out;
+        OP_MULTU:   y = multu_out;
         OP_SLT:     y = {{31{1'b0}}, ($signed(a) < $signed(b))};
         OP_SLTU:    y = {{31{1'b0}}, (a < b)};
         OP_LOAD:    y = b;
@@ -49,8 +67,7 @@ begin
         OP_SHIFTRS: y = $signed(a) >>> b;
         OP_FPMULTS:
         begin
-            ab  = $signed(a) * $signed(b);
-            y   = ab[47:16];
+            y   = mults_out[47:16];
         end      
     endcase
 end

Quartus/modules/CPU/CPU.v

@@ -474,9 +474,10 @@ begin
 end
 
 ALU alu(
+.clk(clk),
 .opcode(aluOP_EX),
-.a(fw_data_a_EX),
-.b(fw_data_b_EX),
+.ax(fw_data_a_EX),
+.bx(fw_data_b_EX),
 .y(alu_result_EX)
 );
 

Quartus/modules/FPGC.v

@@ -131,12 +131,14 @@ clock_pll clkPll(
 );
 */
 
+assign clk = clk_SDRAM;
+
 mainpll mainClkPll(
 .refclk      (clock),
 .rst  		 (1'b0),
 .outclk_0     (clk_SDRAM),
 .outclk_1     (SDRAM_CLK),
-.outclk_2     (clk),
+.outclk_2     (),
 .outclk_3     (clkPixel),
 .outclk_4     (clkTMDShalf)
 );

Quartus/modules/Memory/SRAM.v

@@ -0,0 +1,38 @@
+/*
+* SRAM implementation
+*/
+module SRAM
+#(
+    parameter WIDTH = 32,
+    parameter WORDS = 4096,
+    parameter ADDR_BITS = 12,
+    parameter LIST  = "/home/bart/Documents/FPGA/FPGC6/Verilog/memory/sram.list"
+) 
+(
+  input                   cpu_clk,        
+  input      [WIDTH-1:0]  cpu_d,
+  input      [ADDR_BITS-1:0]       cpu_addr,
+  input                   cpu_we,
+  output reg [WIDTH-1:0]  cpu_q
+);
+
+reg [WIDTH-1:0] ram [0:WORDS-1]; //basically the memory cells
+
+//cpu port
+always @(posedge cpu_clk) 
+begin
+  cpu_q <= ram[cpu_addr];
+  if (cpu_we)
+  begin
+    cpu_q         <= cpu_d;
+    ram[cpu_addr] <= cpu_d;
+  end
+end
+
+//initialize VRAM
+initial 
+begin
+  $readmemb(LIST, ram);
+end
+    
+endmodule

Quartus/modules/Memory/greybox_tmp/cbx_args.txt

@@ -0,0 +1,10 @@
+LPM_HINT=DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=5
+LPM_REPRESENTATION=SIGNED
+LPM_TYPE=LPM_MULT
+LPM_WIDTHA=32
+LPM_WIDTHB=32
+LPM_WIDTHP=64
+DEVICE_FAMILY="Cyclone V"
+dataa
+datab
+result

Quartus/modules/Memory/qmegawiz_errors_log.txt

@@ -0,0 +1,26 @@
+
+
+/home/bart/Documents/FPGA/FPGC6/Quartus/mainpll.v
+
+May 19 05PM:00:55>: Megafunction PLL Intel FPGA IP v23.1 is not listed in any 
+wizard.lst file in the specified library path(s).Wizard launch aborted
+
+/home/bart/Documents/FPGA/FPGC6/Quartus/mainpll.v
+
+May 19 05PM:00:57>: Megafunction PLL Intel FPGA IP v23.1 is not listed in any 
+wizard.lst file in the specified library path(s).Wizard launch aborted
+
+/home/bart/Documents/FPGA/FPGC6/Quartus/mainpll.v
+
+May 19 05PM:23:59>: Megafunction PLL Intel FPGA IP v23.1 is not listed in any 
+wizard.lst file in the specified library path(s).Wizard launch aborted
+
+/home/bart/Documents/FPGA/FPGC6/Quartus/mainpll.v
+
+May 19 05PM:24:01>: Megafunction PLL Intel FPGA IP v23.1 is not listed in any 
+wizard.lst file in the specified library path(s).Wizard launch aborted
+
+/home/bart/Documents/FPGA/FPGC6/Quartus/mainpll.v
+
+May 19 05PM:24:03>: Megafunction PLL Intel FPGA IP v23.1 is not listed in any 
+wizard.lst file in the specified library path(s).Wizard launch aborted

Verilog/memory/sram.list

@@ -1,9 +1,10 @@
 10010000000000000000000000001000 //Jump to constant address 4
-10010000000000000000000000010000 //Jump to constant address 8
+10010000000000000000000000010010 //Jump to constant address 9
 10010000000000000000000000001000 //Jump to constant address 4
 10010000000000000000000000001000 //Jump to constant address 4
 00011100000000000000010100010001 //Set r1 to 5
 00011100000000000000011100100010 //Set r2 to 7
 00000011000000000000000100100011 //Compute r1 + r2 and write result to r3
+11010000000000100101000000110000 //Write value in r3 to address in r0 with offset 37
 11111111111111111111111111111111 //Halt
 01000000000000000000000000000000 //Return from interrupt

Verilog/modules/CPU/CPU.v

@@ -705,7 +705,6 @@ Regr #(.N(3)) regr_cuflags_MEM_WB(
 /*
 * WRITE BACK (WB)
 */
-wire [15:0] const16u_WB;
 
 InstructionDecoder instrDec_WB(
 .instr(instr_WB),
@@ -715,7 +714,7 @@ InstructionDecoder instrDec_WB(
 
 .constAlu(),
 .const16(),
-.const16u(const16u_WB),
+.const16u(),
 .const27(),
 
 .areg(),
@@ -835,7 +834,7 @@ end
 
 always @(posedge clk)
 begin
-    led <= pc_FE[0];
+    led <= (pc_FE != 27'd8);
 end
 
 endmodule

Verilog/output/FPGC.gtkw

@@ -1,15 +1,15 @@
 [*]
 [*] GTKWave Analyzer v3.3.116 (w)1999-2023 BSI
-[*] Sun May 19 13:59:52 2024
+[*] Sun May 19 14:25:27 2024
 [*]
 [dumpfile] "/home/bart/Documents/FPGA/FPGC6/Verilog/output/wave.vcd"
-[dumpfile_mtime] "Sun May 19 13:56:54 2024"
-[dumpfile_size] 757561
+[dumpfile_mtime] "Sun May 19 14:24:28 2024"
+[dumpfile_size] 753014
 [savefile] "/home/bart/Documents/FPGA/FPGC6/Verilog/output/FPGC.gtkw"
 [timestart] 0
 [size] 2560 1361
 [pos] -1 -1
-*-5.400000 121 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-5.400000 122 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] FPGC_tb.
 [treeopen] FPGC_tb.fpgc.
 [treeopen] FPGC_tb.fpgc.cpu.
@@ -25,19 +25,10 @@ FPGC_tb.led
 -
 -Fetch
 @24
-FPGC_tb.fpgc.cpu.pc4_FE[31:0]
-@200
--
-@25
-FPGC_tb.fpgc.cpu.addr_a[31:0]
-@24
-FPGC_tb.fpgc.cpu.data_a[31:0]
-FPGC_tb.fpgc.cpu.we_a
-FPGC_tb.fpgc.cpu.start_a
+FPGC_tb.fpgc.cpu.pc_FE[31:0]
 @28
-FPGC_tb.fpgc.cpu.arbiter_q[31:0]
-@24
-FPGC_tb.fpgc.cpu.done_a
+FPGC_tb.fpgc.cpu.instr_hit_FE
+FPGC_tb.fpgc.cpu.instr_DE[31:0]
 @200
 -
 @28
@@ -46,6 +37,34 @@ FPGC_tb.fpgc.cpu.flush_FE
 @200
 -
 -Decode
+@28
+FPGC_tb.fpgc.cpu.instr_DE[31:0]
+FPGC_tb.fpgc.cpu.instrOP_DE[3:0]
+@24
+FPGC_tb.fpgc.cpu.areg_DE[3:0]
+FPGC_tb.fpgc.cpu.breg_DE[3:0]
+@28
+FPGC_tb.fpgc.cpu.he_DE
+FPGC_tb.fpgc.cpu.oe_DE
+FPGC_tb.fpgc.cpu.sig_DE
+@200
+-
+@28
+FPGC_tb.fpgc.cpu.alu_use_const_DE
+FPGC_tb.fpgc.cpu.push_DE
+FPGC_tb.fpgc.cpu.pop_DE
+FPGC_tb.fpgc.cpu.dreg_we_DE
+FPGC_tb.fpgc.cpu.mem_write_DE
+FPGC_tb.fpgc.cpu.mem_read_DE
+FPGC_tb.fpgc.cpu.jumpc_DE
+FPGC_tb.fpgc.cpu.jumpr_DE
+FPGC_tb.fpgc.cpu.halt_DE
+FPGC_tb.fpgc.cpu.reti_DE
+FPGC_tb.fpgc.cpu.branch_DE
+FPGC_tb.fpgc.cpu.getIntID_DE
+FPGC_tb.fpgc.cpu.getPC_DE
+FPGC_tb.fpgc.cpu.clearCache_DE
+@200
 -
 @28
 FPGC_tb.fpgc.cpu.stall_DE
@@ -53,6 +72,31 @@ FPGC_tb.fpgc.cpu.flush_DE
 @200
 -
 -Execute
+@28
+FPGC_tb.fpgc.cpu.instr_EX[31:0]
+FPGC_tb.fpgc.cpu.aluOP_EX[3:0]
+@420
+FPGC_tb.fpgc.cpu.alu_const16_EX[31:0]
+@25
+FPGC_tb.fpgc.cpu.alu_const16u_EX[31:0]
+@24
+FPGC_tb.fpgc.cpu.areg_EX[3:0]
+FPGC_tb.fpgc.cpu.breg_EX[3:0]
+FPGC_tb.fpgc.cpu.dreg_EX[3:0]
+@200
+-
+@24
+FPGC_tb.fpgc.cpu.alu_input_b_EX[31:0]
+FPGC_tb.fpgc.cpu.fw_data_a_EX[31:0]
+FPGC_tb.fpgc.cpu.fw_data_b_EX[31:0]
+FPGC_tb.fpgc.cpu.alu_result_EX[31:0]
+FPGC_tb.fpgc.cpu.execute_result_EX[31:0]
+@200
+-
+@24
+FPGC_tb.fpgc.cpu.forward_a[1:0]
+FPGC_tb.fpgc.cpu.forward_b[1:0]
+@200
 -
 @28
 FPGC_tb.fpgc.cpu.stall_EX
@@ -60,6 +104,44 @@ FPGC_tb.fpgc.cpu.flush_EX
 @200
 -
 -Memory
+@28
+FPGC_tb.fpgc.cpu.instr_MEM[31:0]
+FPGC_tb.fpgc.cpu.branchOP_MEM[2:0]
+@24
+FPGC_tb.fpgc.cpu.const16_MEM[31:0]
+FPGC_tb.fpgc.cpu.const27_MEM[26:0]
+FPGC_tb.fpgc.cpu.dreg_MEM[3:0]
+@28
+FPGC_tb.fpgc.cpu.oe_MEM
+FPGC_tb.fpgc.cpu.sig_MEM
+@200
+-
+@24
+FPGC_tb.fpgc.cpu.jump_addr_MEM[31:0]
+FPGC_tb.fpgc.cpu.branch_MEM
+@28
+FPGC_tb.fpgc.cpu.branch_passed_MEM
+@200
+-
+@24
+FPGC_tb.fpgc.cpu.dataMem_addr_MEM[31:0]
+@28
+FPGC_tb.fpgc.cpu.mem_write_MEM
+FPGC_tb.fpgc.cpu.mem_read_MEM
+@24
+FPGC_tb.fpgc.cpu.data_b_MEM[31:0]
+FPGC_tb.fpgc.cpu.dataMem_q_WB[31:0]
+@28
+FPGC_tb.fpgc.cpu.datamem_busy_MEM
+@200
+-
+@28
+FPGC_tb.fpgc.cpu.push_MEM
+FPGC_tb.fpgc.cpu.pop_MEM
+@24
+FPGC_tb.fpgc.cpu.data_b_MEM[31:0]
+FPGC_tb.fpgc.cpu.stack_q_WB[31:0]
+@200
 -
 @28
 FPGC_tb.fpgc.cpu.stall_MEM
@@ -67,9 +149,51 @@ FPGC_tb.fpgc.cpu.flush_MEM
 @200
 -
 -Write Back
+@28
+FPGC_tb.fpgc.cpu.instr_WB[31:0]
+@200
+-
+@24
+FPGC_tb.fpgc.cpu.dreg_WB[3:0]
+FPGC_tb.fpgc.cpu.data_d_WB[31:0]
+FPGC_tb.fpgc.cpu.dreg_we_WB
+@200
 -
 @28
 FPGC_tb.fpgc.cpu.stall_WB
 FPGC_tb.fpgc.cpu.flush_WB
+@200
+-
+-
+-Arbiter
+@24
+FPGC_tb.fpgc.cpu.addr_a[31:0]
+FPGC_tb.fpgc.cpu.data_a[31:0]
+FPGC_tb.fpgc.cpu.we_a
+FPGC_tb.fpgc.cpu.start_a
+FPGC_tb.fpgc.cpu.done_a
+@200
+-
+@24
+FPGC_tb.fpgc.cpu.addr_b[31:0]
+FPGC_tb.fpgc.cpu.data_b[31:0]
+FPGC_tb.fpgc.cpu.we_b
+FPGC_tb.fpgc.cpu.start_b
+FPGC_tb.fpgc.cpu.done_b
+@200
+-
+@24
+FPGC_tb.fpgc.cpu.arbiter_q[31:0]
+@200
+-
+@24
+FPGC_tb.fpgc.cpu.arbiter_bus_addr[26:0]
+FPGC_tb.fpgc.cpu.arbiter_bus_data[31:0]
+FPGC_tb.fpgc.cpu.arbiter_bus_we
+FPGC_tb.fpgc.cpu.arbiter_bus_start
+FPGC_tb.fpgc.cpu.arbiter_bus_done
+FPGC_tb.fpgc.cpu.arbiter_bus_q[31:0]
+@200
+-
 [pattern_trace] 1
 [pattern_trace] 0