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# Welcome
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# Welcome
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-[![FPGC Logo](images/logo_big_alpha.png)](https://www.github.com/b4rt-dev/fpgc6)
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+[![FPGC Logo](images/logo_big_alpha.png)](https://www.github.com/bartpleiter/fpgc6)
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!!! warning
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!!! warning
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This Wiki is regularly outdated
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This Wiki is regularly outdated
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@@ -15,7 +15,7 @@ TODO: add picture of FPGC running edit on edit.c
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## New in version 6
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## New in version 6
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-The largest change in the FPGC6 is the complete redesign of the CPU from the [FPGC5](https://github.com/b4rt-dev/FPGC5) with more advanced techniques and performance in mind. The new CPU (built from scratch again) is now a pipelined CPU including hazard detection/forwarding with a better architecture for running C code including better signed integer support. It also allows for L1 cache (although currently not implemented). A lot of inspiration for the CPU is taken from MIPS, because many online resources on more advanced CPU techniques like pipelining and caching use MIPS as example. As for implementation specific inspiration, I looked a lot at [mips-cpu by jmahler](https://github.com/jmahler/mips-cpu), since it is a good example of a simple pipelined CPU.
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+The largest change in the FPGC6 is the complete redesign of the CPU from the [FPGC5](https://github.com/bartpleiter/FPGC5) with more advanced techniques and performance in mind. The new CPU (built from scratch again) is now a pipelined CPU including hazard detection/forwarding with a better architecture for running C code including better signed integer support. It also allows for L1 cache (although currently not implemented). A lot of inspiration for the CPU is taken from MIPS, because many online resources on more advanced CPU techniques like pipelining and caching use MIPS as example. As for implementation specific inspiration, I looked a lot at [mips-cpu by jmahler](https://github.com/jmahler/mips-cpu), since it is a good example of a simple pipelined CPU.
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Version 6 of the FPGC now also contains a better SDRAM controller and cache, which greatly reduces the SDRAM bottleneck.
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Version 6 of the FPGC now also contains a better SDRAM controller and cache, which greatly reduces the SDRAM bottleneck.
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Aside from this and the CPU, all other parts of the system are mostly identical to the FPGC5, and the CPU itself still has all old instructions implemented (although using different opcodes and argument placement) except for COPY. Therefore, after updating the Assembler, almost all code will still work meaning I do not have to rewrite most of my code base.
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Aside from this and the CPU, all other parts of the system are mostly identical to the FPGC5, and the CPU itself still has all old instructions implemented (although using different opcodes and argument placement) except for COPY. Therefore, after updating the Assembler, almost all code will still work meaning I do not have to rewrite most of my code base.
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@@ -32,13 +32,13 @@ Aside from this and the CPU, all other parts of the system are mostly identical
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FPGC6:
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FPGC6:
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-- [Github Repository](https://www.github.com/b4rt-dev/FPGC6)
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+- [Github Repository](https://www.github.com/bartpleiter/FPGC6)
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- [Gogs Mirror](https://www.b4rt.nl/git/bart/FPGC6-mirror)
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- [Gogs Mirror](https://www.b4rt.nl/git/bart/FPGC6-mirror)
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- [Documentation](https://www.b4rt.nl/fpgc)
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- [Documentation](https://www.b4rt.nl/fpgc)
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FPGC5:
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FPGC5:
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-- [Github Repository](https://github.com/b4rt-dev/FPGC5)
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+- [Github Repository](https://github.com/bartpleiter/FPGC5)
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- [Gogs Mirror](https://www.b4rt.nl/git/bart/FPGC5-mirror)
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- [Gogs Mirror](https://www.b4rt.nl/git/bart/FPGC5-mirror)
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- [Documentation](https://www.b4rt.nl/fpgc5)
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- [Documentation](https://www.b4rt.nl/fpgc5)
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